Oxide TFT Aperture Ratio via Cross-Pixel Transistor Layout
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Solution Overview
Problem
The existing array substrates with oxide thin film transistors face challenges in forming a coplanar structure for high definition devices due to the large size of the transistors, which results in a decreased aperture ratio, especially in devices with small display sizes like tablet PCs or cellular phones.
Innovation Solution
The array substrate design includes an oxide semiconductor layer with a bent portion and semiconductor contact holes disposed in two adjacent pixel regions, allowing the oxide thin film transistor to span across two pixel regions, with the source and drain electrodes positioned accordingly to optimize conducting properties and reduce transistor size, thereby increasing the aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a coplanar structure oxide thin film transistor is formed in each pixel region, then the aperture ratio increases, but the transistor size becomes too large for small pixel regions in high definition devices
Solution Approach 1:
The invention divides the transistor structure into two separate regions: the gate electrode is formed in the first pixel region while the source and drain electrodes are formed in the second pixel region. This segmentation allows each component to be optimally positioned in different pixel regions, reducing the overall transistor footprint within a single pixel region while maintaining the coplanar structure benefits for aperture ratio.
2Area of stationary object
If the oxide thin film transistor size is reduced to fit small pixel regions, then the aperture ratio increases, but the conducting properties and performance of the transistor deteriorate
Solution Approach 1:
The invention transitions from a two-dimensional planar arrangement where all transistor components are confined within a single pixel region to a three-dimensional spatial arrangement that utilizes adjacent pixel regions. By extending the transistor structure across pixel region boundaries, the design maintains adequate transistor dimensions for proper conducting properties while increasing the aperture ratio within the original pixel region.
Data Source
AI summary
An array substrate includes a substrate; an oxide semiconductor layer on the substrate, the oxide semiconductor layer including an active area and source and drain areas at both sides of the active area; a gate insulating layer and a gate electrode sequentially on the active area of the oxide semiconductor layer; an inter insulating layer on the gate electrode and having first and second semiconductor contact holes that expose the source and drain areas respectively; and source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first and second semiconductor contact holes, respectively, wherein the first and second semiconductor contact holes are disposed in two regions.