Oxide Semiconductor TFT Doping Layout for Stable Threshold Voltage
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Solution Overview
Problem
Existing display devices face challenges in achieving stable threshold voltage and high resolution due to limitations in semiconductor layer design, particularly in oxide semiconductor layers with short channel lengths.
Innovation Solution
A display device is designed with an oxide semiconductor layer that includes multiple regions with different carrier concentrations, achieved by doping p-type and n-type impurity ions. This structure involves a specific doping process to create regions with varying impurity concentrations, which helps in maintaining a stable threshold voltage and improving resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a short channel length is used in the oxide semiconductor layer, then the resolution of the display device is improved, but the threshold voltage stability deteriorates
Solution Approach 1:
The patent applies local quality by creating multiple regions within the oxide semiconductor layer with different impurity concentrations. Specifically, it forms a first region with a first impurity concentration and a second region with a second impurity concentration that is higher than the first. This spatial variation in doping concentration allows different portions of the semiconductor layer to perform different functions - maintaining threshold voltage stability in doped regions while enabling short channel operation in undoped or lightly-doped channel regions.
Solution Approach 2:
The patent utilizes parameter changes by varying the impurity concentration across different regions of the oxide semiconductor layer. By controlling the doping parameters (impurity type, concentration, and distribution), the patent achieves both short channel length operation and stable threshold voltage. The impurity concentration serves as the key parameter that is changed spatially to resolve the contradiction between resolution and voltage stability.
2Ease of manufacture
If a single impurity doping is used in the oxide semiconductor layer, then the manufacturing process is simple, but the threshold voltage stability and resolution are compromised
Solution Approach 1:
The patent implements local quality through multi-region impurity doping, where different regions of the oxide semiconductor layer receive different impurity concentrations. This creates functionally distinct zones within the semiconductor layer that enable both high resolution and stable threshold voltage, overcoming the limitations of uniform single-impurity doping while maintaining a relatively streamlined manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively stabilizes the threshold voltage and enhances the resolution of display devices by utilizing an oxide semiconductor layer with carefully designed impurity doping, thereby improving the reliability and display quality of the devices.
Implementation Method 1
A second oxide semiconductor layer may include a channel region and a source region disposed on a first side of the channel region and a drain region disposed on s second side of the channel region. The source region may include a first source region disposed adjacent to the channel region and a second source region disposed adjacent to the first source region, and the drain region include a first drain region disposed adjacent to the channel region and a second drain region disposed adjacent to the first drain region. Each of the first source region and the first drain region may include a first impurity ion, and each of the second source region and the second drain region includes a second impurity ion which are different from the first impurity.
Data Source
AI summary
A display device according to an embodiment includes a substrate and a transistor including an oxide semiconductor layer and a gate electrode disposed on the oxide semiconductor layer. The oxide semiconductor layer includes a channel region and a first source region disposed adjacent to the channel region and a second source region disposed adjacent to the first source region, and the drain region include a first drain region disposed adjacent to the channel region and a second drain region disposed adjacent to the first drain region. Each of the first source region and the first drain region includes a first impurity ion, and each of the second source region and the second drain region includes a second impurity ion which are different from the first impurity.