Dual-Layer Light Shielding for Oxide TFT Display Stability
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Solution Overview
Problem
Transistors using oxide semiconductors as channels are prone to characteristic fluctuations due to light exposure, which can hinder high-definition displays, and the light-shielding layers in existing configurations are insufficient to prevent this, especially when combined with low-temperature polysilicon transistors in peripheral circuits.
Innovation Solution
A display device design featuring a dual-layer light-shielding structure with a first light-shielding metal layer under the oxide semiconductor and a second layer covering its top and side surfaces, along with a thicker light-shielding layer in peripheral transistors, to shield light effectively and stabilize transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a light-shielding layer is provided under the oxide semiconductor transistor to prevent light exposure, then the characteristic fluctuation of the oxide semiconductor is suppressed, but the light-shielding layer thickness must be increased which conflicts with the gate electrode thickness requirement for LTPS transistors in peripheral circuits
Solution Approach 1:
The light-shielding layer is divided into two separate metal layers (first light-shielding metal layer and second light-shielding metal layer) with different thicknesses and positions. The first layer is positioned under the oxide semiconductor transistor with greater thickness for strong light shielding, while the second layer is positioned under the LTPS transistor with smaller thickness to satisfy gate electrode thickness requirements, thus resolving the contradiction between light shielding effectiveness and thickness constraints.
Solution Approach 2:
Different regions of the light-shielding structure are assigned different thicknesses based on local requirements. The region under the oxide semiconductor transistor has a thicker first light-shielding metal layer to prevent characteristic fluctuation, while the region under the LTPS transistor has a thinner second light-shielding metal layer to meet gate electrode thickness specifications, achieving localized optimization.
2Manufacturing precision
If the pixel size is reduced to achieve high-definition displays, then the display resolution is improved, but the opening ratio of the pixel is reduced due to the arrangement of metal and semiconductor layers
Solution Approach 1:
The light-shielding function is extended from a single planar layer to a three-dimensional structure with multiple layers at different heights and positions. This vertical dimensionality allows the light-shielding layers to be arranged more efficiently in the thickness direction, reducing their horizontal footprint and thereby increasing the pixel opening ratio while maintaining high-definition display capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-layer light-shielding design suppresses oxide semiconductor transistor fluctuations, enabling high-definition displays by maintaining stable performance and reducing light exposure effects.
Implementation Method 1
a light-shielding layer provided between the substrate and the oxide semiconductor layer
Data Source
AI summary
A display device includes a substrate, a first transistor including an oxide semiconductor layer, a first gate insulating layer, and a first gate electrode, the first transistor being provided in a display region, and a light-shielding layer provided between the substrate and the oxide semiconductor layer. The light-shielding layer includes a first light-shielding metal layer and a second light-shielding metal layer. The first light-shielding metal is provided between the substrate and the oxide semiconductor layer. The second light-shielding metal layer covers the top surface and side surface of the first light-shielding metal layer and faces the oxide semiconductor layer.