Oxide TFT Gate Layout to Prevent ESD Leakage in Pixel Substrates
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Solution Overview
Problem
In active matrix substrates with oxide semiconductor TFTs, Electro-Static Discharge (ESD) during the manufacturing process can cause leakage between the source and gate electrodes, reducing yield and making it difficult to increase the thickness of the insulating layer to prevent such leakage.
Innovation Solution
The active matrix substrate design includes a top gate structure with a gate electrode separated from the gate bus lines and covered by an interlayer insulating layer, featuring gate contact holes that expose parts of the gate electrode for electrical connection, reducing the risk of ESD and leakage by minimizing the electric charge accumulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the insulating layer thickness is increased to prevent ESD-induced leakage, then reliability improves, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The gate electrode is segmented from the gate bus line by introducing a gate contact hole structure. This segmentation isolates the gate electrode in the pixel area from the extended gate bus line, preventing ESD propagation from the bus line to the oxide semiconductor layer while maintaining electrical connection where needed. The gate electrode and gate bus line are separated by an insulating layer with contact holes, creating distinct functional zones.
Solution Approach 2:
An insulating layer with gate contact holes serves as an intermediary between the gate electrode and gate bus line. This intermediate structure allows controlled electrical connection through the contact holes while providing ESD protection in other areas, effectively mediating between the need for electrical connectivity and the need for ESD prevention.
2Reliability
If the gate electrode is separated from gate bus lines to prevent ESD, then reliability improves, but device complexity increases
Solution Approach 1:
The gate electrode is segmented from the gate bus line by introducing a gate contact hole structure. This segmentation isolates the gate electrode in the pixel area from the extended gate bus line, preventing ESD propagation from the bus line to the oxide semiconductor layer while maintaining electrical connection where needed.
Solution Approach 2:
The separation is achieved in the vertical dimension by using an insulating layer and gate contact holes, rather than horizontal separation. This allows the gate electrode and gate bus line to be separated in the Z-direction (through the insulating layer) while maintaining planar integration, reducing the complexity increase.
3Reliability
If gate contact holes are introduced to expose gate electrode, then electrical connection is improved, but manufacturing precision requirements increase
Solution Approach 1:
The gate contact holes are formed in the insulating layer before the gate electrode is deposited. This preliminary action establishes the connection pathways in advance, allowing the gate electrode to be precisely positioned within the predefined contact hole areas, thereby reducing the overall alignment complexity during subsequent manufacturing steps.
Data Source
AI summary
An active matrix substrate includes a plurality of source bus lines, a lower insulating layer covering the source bus lines, a plurality of gate bus lines formed above the lower insulating layer, and an oxide semiconductor TFT disposed to correspond to each pixel area. The oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, and a gate electrode disposed above the oxide semiconductor layer. The gate electrode is formed in a different layer from the gate bus lines, and is disposed to be separated from another gate electrode disposed in an adjacent pixel area. The gate electrode is covered by an interlayer insulating layer. The gate bus line is disposed on the interlayer insulating layer and in a gate contact hole formed in the interlayer insulating layer, and is connected to the gate electrode in the gate contact hole.