Oxide TFT Electrode Layout With Fewer Mask Processes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The fabrication of transistor array substrates with thin-film transistors is costly and yields are low due to the high number of mask processes, leading to unreliable and non-uniform current characteristics.
Innovation Solution
A thin-film transistor design with an active layer made of an oxide semiconductor in a crystalline phase, integrated with a gate electrode, source electrode, and drain electrode formed as a single unit, reducing the number of mask processes while maintaining reliability and uniformity by using heat treatment and etching with fluorine-containing materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of mask processes is increased to fabricate thin-film transistors, then the manufacturing precision and reliability of current characteristics are improved, but the fabrication cost increases and yield decreases
Solution Approach 1:
The patent merges the gate electrode, source electrode, and drain electrode into a single conductive layer structure. This allows all three electrodes to be formed simultaneously in one mask process rather than requiring separate mask processes for each electrode, thereby reducing the total number of mask processes while maintaining the precision needed for reliable current characteristics
Solution Approach 2:
The conductive layer serves multiple functions simultaneously by forming the gate electrode, source electrode, and drain electrode all in one layer. This multi-functional approach eliminates the need for multiple specialized mask processes, reducing fabrication cost and improving yield while maintaining manufacturing precision
2Ease of manufacture
If the number of mask processes is reduced to lower fabrication cost, then the ease of manufacture is improved, but the manufacturing precision and reliability of current characteristics deteriorate
Solution Approach 1:
By combining the formation of gate, source, and drain electrodes into a single mask process, the patent achieves cost reduction without sacrificing precision. The merged structure is designed so that one mask pattern can define all three electrodes with the required accuracy for reliable current characteristics
Solution Approach 2:
The patent transitions from a multi-layer electrode structure requiring multiple mask processes to a single-layer conductive structure. This dimensional simplification reduces the number of mask processes needed while maintaining the functional precision of individual electrodes through optimized in-plane positioning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method allows for the fabrication of thin-film transistors with high reliability and uniformity of current characteristics using fewer mask processes, resulting in cost-effective and efficient transistor array substrates.
Implementation Method 1
The active layer includes an oxide semiconductor including crystals by heat treatment
Implementation Method 2
an oxide semiconductor including crystals by heat treatment
Implementation Method 3
etching with fluorine-containing materials
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.