Oxide TFT Array Substrate Gate Barrier Layer Design
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Solution Overview
Problem
The existing array substrates using amorphous silicon TFTs face limitations in charge carrier mobility, leading to reliability issues and increased defect rates due to grain growth and cavity formation in the gate electrodes, which affect the performance and durability of display devices, especially as the size and resolution of flat panel displays increase.
Innovation Solution
The introduction of a gate barrier layer exposed through a gate open portion and the removal of source and drain electrodes with data and drain barrier layers exposed through respective open portions, preventing grain growth and cavity formation, and improving the reliability of the oxide thin film transistor array substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heat treatment processes are performed for fabricating the oxide TFT, then the oxide TFT can be formed, but grain growth and cavity formation occur in the copper gate electrode
Solution Approach 1:
A barrier layer is formed on the copper gate electrode before heat treatment processes. This preliminary protective layer prevents copper atoms from migrating and forming grains during subsequent heat treatment steps, thereby maintaining gate electrode composition stability while enabling oxide TFT fabrication
Solution Approach 2:
The barrier layer acts as an intermediary between the copper gate electrode and the heat treatment process. It mediates the interaction by blocking copper atom diffusion during heating, preventing grain growth and cavity formation while allowing the heat treatment to proceed for oxide TFT formation
2Power
If the gate electrode is formed of copper with low resistance and high electrical conductivity, then the gate line performance is improved, but grain growth and cavity formation occur due to heat treatment
Solution Approach 1:
The barrier layer is deposited on the copper gate electrode before any heat treatment processes. This preliminary protective structure enables the use of copper for its excellent electrical conductivity while preventing the structural degradation (grain growth and cavities) that would otherwise occur during subsequent heating steps
Solution Approach 2:
The barrier layer converts the harmful effect of heat treatment (which causes grain growth in copper) into a beneficial process. By blocking copper diffusion, it allows heat treatment to proceed without damaging the gate electrode structure, thus enabling both high conductivity and structural reliability
3Ease of manufacture
If amorphous silicon TFT is used, then the manufacturing process is simpler, but the charge carrier mobility is limited to about 1 cm2/Vsec
Solution Approach 1:
The semiconductor material parameter is changed from amorphous silicon to oxide semiconductor. This material substitution increases charge carrier mobility from about 1 cm2/Vsec to significantly higher values while maintaining compatibility with low-temperature fabrication processes, thus improving speed without sacrificing ease of manufacture
Data Source
AI summary
An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.