Oxide TFT Gate Driver Layout for Lower-Power Display Panels
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Solution Overview
Problem
Existing display panels face challenges in achieving reduced power consumption and improved display quality, particularly in multimedia electronic devices.
Innovation Solution
The display panel incorporates a first and second driving circuit with oxide semiconductor transistors, a conductive pattern, and a dummy semiconductor pattern, along with an intermediate insulation layer and clock lines, to optimize signal transmission and reduce power consumption while enhancing display quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor transistors are used in driving circuits, then display quality is improved, but power consumption increases
Solution Approach 1:
The patent extracts and removes the dummy semiconductor pattern from the active circuit area and places it in the non-display area. This separation allows the dummy pattern to serve as a stress relief structure without consuming active circuit space or increasing power consumption, while still maintaining display quality through the stress relief function.
Solution Approach 2:
The patent introduces an intermediate insulation layer between the dummy semiconductor pattern and the oxide semiconductor layer. This intermediary structure isolates the dummy pattern electrically while allowing it to provide mechanical stress relief, thus preventing direct electrical connection that would increase power consumption while maintaining the beneficial stress relief effect.
2Manufacturing precision
If dummy semiconductor pattern is added for stress relief, then manufacturing quality is improved, but device complexity increases
Solution Approach 1:
The patent merges the dummy semiconductor pattern with the existing insulation layer structure by positioning the dummy pattern on the insulation layer in the non-display area. This integration approach allows the dummy pattern to serve dual purposes: stress relief for the oxide semiconductor layer and structural support, without adding separate complex structures.
Solution Approach 2:
The patent positions the dummy semiconductor pattern in the vertical dimension (on the insulation layer above the substrate) rather than in the horizontal circuit plane. This dimensional relocation allows the dummy pattern to provide stress relief without occupying active circuit space, thus reducing overall device complexity.
3Reliability
If conductive pattern is placed adjacent to oxide semiconductor layer, then hydrogen abstraction is improved, but risk of threshold voltage shift increases
Solution Approach 1:
The patent introduces an intermediate insulation layer as a mediator between the conductive pattern and the oxide semiconductor layer. This intermediary structure allows hydrogen from the conductive pattern to be abstracted by the oxide semiconductor layer while preventing direct electrical contact that would cause threshold voltage shifts, thus maintaining both hydrogen abstraction benefits and voltage stability.
Data Source
AI summary
Disclosed is a display panel including a first driving circuit including first stages arranged along a first direction, a second driving circuit including second stages arranged along the first direction, and at least one clock line between the first driving circuit and the second driving circuit, and extending along the first direction, wherein the first stages and the second stages include an oxide semiconductor transistor including an oxide semiconductor layer, and a gate electrode overlapping portions of the oxide semiconductor layer, and a conductive pattern adjacent to the oxide semiconductor transistor, and at a same layer as the gate electrode.