Gate Insulator Openings in Oxide TFT Displays for Contact Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing display devices face challenges in maintaining reliability and uniform ion concentration at transistor contacts due to oxygen diffusion, affecting the performance and longevity of the display elements.
Innovation Solution
The display device incorporates a design with oxide semiconductor patterns and strategically formed open areas in the gate insulating layer to expose transistor sources and drains, ensuring uniform ion concentration and improved electrical connections through wider opened portions for better oxygen diffusion control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating layer is made continuous without open areas, then the insulation performance is improved, but the ion concentration uniformity at transistor contacts deteriorates due to poor oxygen diffusion
Solution Approach 1:
The gate insulating layer is segmented by forming open areas at the source and drain regions, allowing oxygen to diffuse through these openings to achieve uniform ion concentration at the transistor contacts, while maintaining insulation performance in the channel region
Solution Approach 2:
Different regions of the gate insulating layer are treated differently: open areas are formed at source and drain regions to enable oxygen diffusion and uniform ion concentration, while the channel region maintains a continuous insulating structure for proper insulation performance
2Manufacturing precision
If open areas are formed in the gate insulating layer, then the oxygen diffusion and ion concentration uniformity are improved, but the insulation performance deteriorates
Solution Approach 1:
The gate insulating layer is selectively segmented only at source and drain regions where open areas are formed, while the channel region maintains continuous insulation, thus achieving local oxygen diffusion without compromising overall insulation performance
Solution Approach 2:
The gate insulating layer exhibits different structural qualities at different locations: open areas at source/drain for oxygen diffusion, and continuous structure at channel for insulation, resolving the contradiction between diffusion and insulation requirements
3Manufacturing precision
If the contact holes are made narrower to improve alignment precision, then the manufacturing precision is improved, but the oxygen diffusion efficiency deteriorates
Solution Approach 1:
The gate insulating layer is segmented to form open areas that are wider than contact holes, creating dedicated oxygen diffusion pathways that are not constrained by contact hole dimensions, thus improving oxygen diffusion efficiency without compromising alignment precision
Solution Approach 2:
The solution moves from the vertical dimension (contact hole depth) to the horizontal dimension (open area width) for oxygen diffusion, creating wider pathways at the gate insulating layer level that facilitate better oxygen diffusion while maintaining precise alignment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and screen characteristics of the display device by maintaining uniform ion concentration at transistor contacts, thereby improving the overall performance and longevity of the display elements.
Implementation Method 1
an open area through the gate insulating layer corresponds to a first source and a first drain of the first oxide semiconductor pattern
Data Source
AI summary
A display device includes a base layer, a pixel circuit disposed on the base layer and comprising a plurality of pixel transistors, a gate insulating layer covering the first and second oxide semiconductor patterns, and a light emitting element electrically connected to the pixel circuit. The pixel transistors include a first pixel transistor including a first oxide semiconductor pattern and a second pixel transistor including a second oxide semiconductor pattern. An open area is defined through the gate insulating layer to correspond to a first source and a first drain of the first oxide semiconductor pattern.