Oxide Semiconductor TFT with Minimized Gate Overlap
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Solution Overview
Problem
Conventional methods for manufacturing thin film transistors (TFTs) face challenges such as low mobility with amorphous silicon, high threshold voltage variability with polysilicon, and costly processes like laser heat treatment, making it difficult to implement high-speed driver circuits and scale to large substrates.
Innovation Solution
A method involving the formation of a TFT substrate with a gate electrode, gate insulating layer, and an oxide semiconductor pattern, where the oxide semiconductor layer is patterned using multiple photoresist patterns and plasma treatment to enhance conductivity, and source and drain electrodes are formed to minimize overlap with the gate electrode, thereby improving TFT performance and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as the active layer, then the manufacturing process is simple, but the mobility is low making high-speed driver circuits difficult to implement
Solution Approach 1:
The patent changes the material parameter from conventional amorphous silicon to oxide semiconductor (such as IGZO - indium gallium zinc oxide), which fundamentally alters the electrical properties including carrier mobility and threshold voltage characteristics, enabling high-speed operation while maintaining low-temperature processing advantages
2Speed
If polysilicon is used as the active layer, then the mobility is high, but the threshold voltage is non-uniform requiring separate compensation circuits
Solution Approach 1:
The patent transitions from polysilicon to oxide semiconductor material, which inherently provides uniform threshold voltage characteristics due to its wide bandgap and reduced defect states, eliminating the need for compensation circuits while maintaining high mobility
3Speed
If LTPS process is used to manufacture TFT, then the mobility is high, but costly processes such as laser heat treatment are required increasing investment costs
Solution Approach 1:
The patent changes the material system to oxide semiconductor which can be processed at lower temperatures without requiring laser annealing or rapid thermal processing, thereby eliminating expensive equipment investments and reducing manufacturing costs while achieving comparable or superior performance
Solution Approach 2:
The oxide semiconductor process uses conventional low-cost sputtering or atomic layer deposition equipment without requiring expensive laser systems or rapid thermal annealing facilities, making the manufacturing process more accessible and cost-effective
4Speed
If LTPS process is used to manufacture TFT, then the mobility is high, but it is difficult to scale to large substrates
Solution Approach 1:
The patent adopts oxide semiconductor material that can be deposited uniformly over large substrate areas using sputtering or ALD techniques without the need for laser scanning or rapid thermal processing, enabling scalable manufacturing on large-sized substrates while maintaining high mobility characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of TFTs with improved conductivity and reduced kickback voltage, preventing a decrease in current flow and pixel charging rate, while being more cost-effective and scalable to larger substrates.
Implementation Method 1
making the first region and the second region be conductive by using a second photoresist pattern
Data Source
AI summary
Provided is a method of manufacturing TFT substrate, the method including: forming a first conductive layer and a gate electrode; forming a gate insulating layer covering the first conductive layer and the gate electrode; forming a first contact hole exposing the first conductive layer through the gate insulating layer; forming, on the gate insulating layer of a pixel area, an oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, and a third region between the first region and the second region; forming a source electrode contacting the first region of the oxide semiconductor pattern, a drain electrode contacting the second region of the oxide semiconductor pattern and a second conductive layer contacting the first conductive layer on a non-pixel area. Each of the first region and the second region overlaps the gate electrode.