Oxide Semiconductor TFT Gate Electrode Recesses for Parasitic Capacitance Reduction
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Solution Overview
Problem
Oxide semiconductor TFTs have lower current driving power compared to polycrystalline silicon TFTs, requiring larger channel widths and increased size, which complicates the reduction of non-display areas in active matrix substrates, and parasitic capacitances become significant issues when reducing TFT size.
Innovation Solution
The active matrix substrate incorporates a TFT design with recessed or protruding portions on the gate electrodes, overlapping with the oxide semiconductor layer, to reduce parasitic capacitances and allow for smaller TFT sizes while maintaining desired characteristics, including a double gate structure with recessed or protruding portions on both gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If oxide semiconductor TFT is used to replace polycrystalline silicon TFT, then manufacturing simplicity is improved, but current driving power decreases and TFT size increases
Solution Approach 1:
The patent changes the material parameter from oxide semiconductor to polycrystalline silicon for the activation layer, which fundamentally alters the electrical characteristics including carrier mobility and current driving capability. This material substitution resolves the contradiction by maintaining the manufacturing simplicity of thin-film processes while achieving the higher current driving power required for SSD circuit TFTs.
2Reliability
If oxide semiconductor TFT is used for SSD circuit, then manufacturing consistency is improved, but TFT size increases due to lower mobility
Solution Approach 1:
The patent changes the material parameter from oxide semiconductor to polycrystalline silicon for the activation layer. This material substitution provides higher carrier mobility, which allows the TFT to achieve the required current driving capability in a smaller area, thus resolving the contradiction between manufacturing consistency and TFT size reduction.
3Area of stationary object
If TFT size is reduced to narrow non-display area, then area efficiency is improved, but parasitic capacitances become significant and degrade performance
Solution Approach 1:
The patent changes the material parameter from oxide semiconductor to polycrystalline silicon, which provides higher carrier mobility. This allows the TFT to be scaled down in size while maintaining adequate current driving capability, thereby reducing the impact of parasitic capacitances and enabling area-efficient design.
Solution Approach 2:
The patent introduces a dual-gate structure that adds a vertical dimension to the transistor design. By controlling the channel from both top and bottom gates, the invention achieves better electrostatic control and higher current density in a compact footprint, effectively managing parasitic capacitances while maintaining performance.
Data Source
AI summary
An active matrix substrate includes a peripheral circuit including a TFT (30A) supported on a substrate (1). When viewed in a direction normal to the substrate (1), a first gate electrode (3) of the TFT (30A) includes a first edge portion and a second edge portion (3e1, 3e2) opposing each other. The first edge portion and the second edge portion extend across an oxide semiconductor layer (7) in a channel width direction. At least one of the first edge portion and the second edge portion includes, in a region overlapping with the oxide semiconductor layer (7), a first recess portion (40) recessed in a channel length direction and a first part (41) adjacent to the first recess portion in the channel width direction. When viewed in the direction normal to the substrate (1), a source electrode (8) or a drain electrode (9) of the TFT (30A) overlaps with at least a part of the first recess portion (40) and at least a part of the first part (41).