Oxide TFT GOLD Structure Using Aluminum Oxide and Overlap Doping
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Solution Overview
Problem
The challenge is to form a gate overlapped lightly doped drain (GOLD) structure in thin film transistors using oxide semiconductors without increasing the number of manufacturing steps, while maintaining high resistance in the channel region and low resistance in the source and drain regions to prevent drain deterioration due to high electric fields.
Innovation Solution
The implementation involves forming a semiconductor device with a channel region, drain region, source region, and low concentration regions using an oxide semiconductor, where an aluminum oxide film is used to enhance resistance and a gate electrode is patterned to overlap the low concentration regions, allowing for ion implantation to impart conductivity without increasing the number of manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a GOLD structure is formed in thin film transistors using oxide semiconductors, then drain deterioration is prevented and transistor reliability is improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines the gate electrode formation process with the LDD region formation process by using a single gate electrode that overlaps both the channel region and the low concentration regions. This integration eliminates the need for separate LDD formation steps while maintaining the protective GOLD structure, thereby improving transistor reliability without increasing manufacturing complexity
Solution Approach 2:
The gate electrode serves multiple functions: it controls the channel region for transistor switching and simultaneously protects the drain region from deterioration through the overlapping low concentration regions. This multi-functionality allows the GOLD structure to be implemented without adding dedicated components or steps, resolving the contradiction between reliability improvement and manufacturing simplicity
2Reliability
If the channel region maintains high resistance, then leakage current is reduced, but ON current decreases
Solution Approach 1:
The patent implements spatially varying impurity concentrations within the semiconductor layer: the channel region maintains high resistance with low impurity concentration to reduce leakage, while the source and drain regions have low resistance with high impurity concentration to ensure strong ON current. This local differentiation allows simultaneous optimization of both leakage control and drive current
Solution Approach 2:
The semiconductor layer is segmented into distinct functional regions with different electrical properties: the channel region for high resistance and low leakage, and the source/drain regions for low resistance and high current capability. This segmentation enables independent optimization of each region's electrical characteristics to satisfy contradictory requirements
3Productivity
If the gate length is shortened to increase transistor density, then device integration is improved, but drain deterioration occurs due to high electric fields
Solution Approach 1:
The patent extends the gate electrode in the vertical dimension to overlap the low concentration regions adjacent to the drain, creating a three-dimensional protective structure. This dimensional extension allows short gate lengths for high density while maintaining drain protection through the overlapping configuration, effectively resolving the contradiction between integration and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of thin film transistors with a GOLD structure that maintains high channel resistance and low source and drain resistance, effectively preventing drain deterioration even in short gate length transistors, while reducing the complexity of the manufacturing process.
Implementation Method 1
forming an aluminum oxide film on the gate insulating film so as to make resistance of the oxide semiconductor high with oxygen
Implementation Method 2
forming a gate electrode on the gate insulating film and on the aluminum oxide film selectively patterned and thereby making the gate electrode suck up the oxygen in the drain region, the source region, and the low concentration regions
Implementation Method 3
performing ion implantation by using the gate electrode selectively patterned as a mask and thereby imparting electroconductivity to the drain region and the source region
Data Source
AI summary
A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.