Oxide TFT Insulating Stack for Hydrogen Diffusion Control
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Solution Overview
Problem
Existing display devices face challenges in achieving improved device characteristics for thin film transistors, particularly due to variations in crystal direction, size, and defects of the polycrystalline silicon film, which affect the performance of thin film transistors in display devices.
Innovation Solution
A display device structure incorporating an oxide semiconductor layer with a specific gate insulating layer and interlayer insulating layers, including silicon oxide and silicon nitride layers with controlled hydrogen concentrations, is used to enhance the device characteristics of thin film transistors. This structure includes a base substrate with an oxide semiconductor layer, a gate insulating layer, and multiple interlayer insulating layers with varying hydrogen concentrations to minimize hydrogen ion diffusion and improve transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polycrystalline silicon film is used to form the channel region and source/drain regions of the thin film transistor, then the transistor can be formed with standard fabrication processes, but the device characteristics vary due to crystal direction, crystal size, and crystal defects
Solution Approach 1:
The patent changes the material parameter from polycrystalline silicon to oxide semiconductor, fundamentally altering the physical and electrical properties of the semiconductor layer. This enables more consistent device characteristics by eliminating crystal structure variations while maintaining compatibility with thin film transistor fabrication processes
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including oxide semiconductor layer, gate insulating layer, and interlayer insulating layers. This multi-layer composite approach allows optimization of each layer's properties to achieve both ease of manufacture and reliable device characteristics
2Device complexity
If conventional gate insulating layers and interlayer insulating layers are used, then the manufacturing process is simple, but hydrogen ion diffusion occurs which degrades transistor performance
Solution Approach 1:
The patent applies different materials with specific properties to different locations in the device structure. The gate insulating layer uses a material with low hydrogen ion concentration near the oxide semiconductor interface, while interlayer insulating layers use materials with progressively higher hydrogen concentrations farther from the interface, optimizing both performance and manufacturability
Solution Approach 2:
The patent changes the hydrogen concentration parameter of the insulating layers by selecting specific materials (such as silicon oxide with controlled hydrogen content, silicon nitride, etc.). This parameter control prevents hydrogen ion diffusion into the oxide semiconductor while maintaining the insulating function and compatibility with standard fabrication processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure enhances the device characteristics of thin film transistors by reducing hydrogen ion diffusion and improving the threshold voltage and mobility, leading to more reliable and efficient operation of the display devices.
Implementation Method 1
hydrogen concentration in the second upper interlayer insulating layer is less than hydrogen concentration in the third upper interlayer insulating layer
Data Source
AI summary
A display device includes a base substrate; an oxide semiconductor layer disposed on the base substrate; a first gate insulating layer disposed on a first channel region of the oxide semiconductor layer and that overlaps the first channel region thereof; a first upper gate electrode disposed on the first gate insulating layer; and an upper interlayer insulating layer disposed on the first upper gate electrode, the first upper gate electrode, and the oxide semiconductor layer, wherein the upper interlayer insulating layer includes a first upper interlayer insulating layer, a second upper interlayer insulating layer, and a third upper interlayer insulating layer, the first upper interlayer insulating layer includes silicon oxide, each of the second and third upper interlayer insulating layers include silicon nitride, and a hydrogen concentration in the second upper interlayer insulating layer is less than a hydrogen concentration in the third upper interlayer insulating layer.