Oxide TFT Active Matrix Substrate Insulation for Leakage Control
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Solution Overview
Problem
The active matrix substrate with oxide semiconductor TFTs in a top gate structure experiences reduced yield and reliability due to decreased breakdown voltage and leakage current in regions with openings in the interlayer and upper insulating layers.
Innovation Solution
The substrate employs a layered structure for interlayer and upper insulating layers, including silicon oxide and silicon nitride layers, with specific thicknesses and configurations to maintain the integrity of the interlayer insulating layer, preventing breakdown voltage reduction and leakage current generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If openings are formed in the organic insulating layer and upper insulating layer to access the intersection region, then manufacturing accessibility is improved, but the breakdown voltage between gate metal layer and source metal layer decreases and leakage current increases
Solution Approach 1:
The interlayer insulating layer is divided into multiple functional layers: a lower layer (first layer) for basic insulation, an intermediate layer (second layer) with high etch resistance to protect against overetching, and an upper layer (third layer) for additional insulation. This segmentation allows the opening to be formed through the organic insulating layer and upper insulating layer while the intermediate layer maintains the breakdown voltage by preventing etching penetration.
Solution Approach 2:
The intermediate layer formed of silicon nitride acts as a mediator between the lower and upper layers. It specifically resists overetching during the formation of openings, thereby protecting the intersection region where the gate metal layer and source metal layer overlap, and maintains the breakdown voltage while still allowing the opening to be formed for manufacturing accessibility.
2Device complexity
If a simple single-layer insulating structure is used, then device complexity is reduced, but the breakdown voltage decreases and leakage current increases at metal layer intersections
Solution Approach 1:
The interlayer insulating layer uses a composite structure combining silicon oxide (lower layer), silicon nitride (intermediate layer), and silicon oxide (upper layer). Each material contributes specific properties: silicon oxide provides insulation and etch resistance, while silicon nitride provides high etch resistance to prevent overetching. This composite structure achieves high breakdown voltage and low leakage current without excessive complexity.
Solution Approach 2:
The intermediate layer is specifically positioned at the critical region where openings are formed and where the gate metal layer and source metal layer intersect. This local placement of the etch-resistant silicon nitride layer provides targeted protection at the most vulnerable points, maintaining breakdown voltage without requiring the entire insulating structure to be overly complex.
Data Source
AI summary
An active matrix substrate includes a pixel TFT including an oxide semiconductor layer, a gate insulating layer provided on the oxide semiconductor layer, and a gate electrode disposed so as to face the oxide semiconductor layer with the gate insulating layer interposed therebetween, a plurality of gate lines, an interlayer insulating layer provided so as to cover the gate electrode and the plurality of gate lines, a plurality of source lines provided on the interlayer insulating layer, an upper insulating layer provided so as to cover the plurality of source lines, and an organic insulating layer provided on the upper insulating layer. The interlayer insulating layer includes a first layer formed of silicon oxide, a second layer provided on the first layer and formed of silicon nitride, and a third layer provided on the second layer and formed of silicon oxide.