Oxide Semiconductor TFT Stack With Interfacial Layer Isolation
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Solution Overview
Problem
Existing semiconductor devices, such as thin film transistors, face challenges in achieving optimal performance due to limitations in material compatibility, processing conditions, and integration with various substrates, particularly in maintaining device characteristics and preventing metallic element diffusion.
Innovation Solution
The method involves forming semiconductor structures with a gate electrode, gate dielectric layer, and oxide semiconductor layers, including a blocking or interfacial layer to prevent metallic element diffusion, and using a dual damascene process for metal interconnects, which enhances electrical isolation and device stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a thin film transistor is formed with conventional materials and processes, then manufacturing cost is reduced and room temperature processing is enabled, but device performance and stability deteriorate due to metallic element diffusion and poor material compatibility
Solution Approach 1:
An interfacial layer is introduced between the oxide semiconductor layer and the gate dielectric layer to prevent direct contact and interaction between these layers. This intermediary layer blocks metallic element diffusion from the gate dielectric into the oxide semiconductor, thereby maintaining device stability and performance while allowing the use of conventional low-cost materials and room temperature processing
Solution Approach 2:
The patent employs a composite structure consisting of multiple functional layers including oxide semiconductor layer, gate dielectric layer, and interfacial layer. Each layer is specifically designed with particular material properties to address different requirements: the oxide semiconductor provides semiconducting function, the gate dielectric provides insulation, and the interfacial layer provides diffusion barrier functionality. This composite approach enables both low-cost manufacturing and high device reliability
2Use of energy by moving object
If oxide semiconductor layers are used for thin film transistors, then room temperature manufacturing and high mobility are achieved, but metallic element diffusion occurs between layers leading to device degradation
Solution Approach 1:
The interfacial layer serves as a diffusion barrier that prevents metallic elements from diffusing between the oxide semiconductor layer and gate dielectric layer. This intermediary structure maintains the compositional stability of each layer while enabling room temperature processing that would otherwise cause material degradation and unwanted diffusion
3Device complexity
If conventional gate dielectric layers are used with oxide semiconductors, then manufacturing simplicity is maintained, but device characteristics deteriorate due to direct interaction and diffusion between layers
Solution Approach 1:
The interfacial layer is positioned between the gate dielectric and oxide semiconductor to prevent direct interaction between these layers. This additional layer, while increasing structural complexity, provides precise control over device characteristics by blocking unwanted diffusion and interaction, thereby improving manufacturing precision and device performance
Solution Approach 2:
The interfacial layer is specifically placed at the critical interface region where diffusion and unwanted interactions occur. This localized approach addresses the specific problem area without requiring changes to the entire device structure, maintaining overall simplicity while providing precise control at the critical interface
Data Source
AI summary
A method of forming a semiconductor device is provided. A gate electrode is formed within an insulating layer that overlies a substrate. A gate dielectric layer is formed over the gate electrode. A first oxide semiconductor layer is formed over the gate dielectric layer. A dielectric layer is formed over the first oxide semiconductor layer. The dielectric layer and the first oxide semiconductor layer are patterned, so as to form first and second openings that expose portions of the gate dielectric layer. An interfacial layer is conformally formed on sidewalls and bottoms of the first and second openings. A second oxide semiconductor layer is formed over the interfacial layer in the first and second openings. A metal layer is formed over the second oxide semiconductor layer in the first and second openings.