Oxide Thin-Film Transistor Liner Structure for BEOL 3D Integration
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Solution Overview
Problem
Current methods for fabricating 3D semiconductor devices are costly and inefficient, particularly in integrating BEOL-compatible components, which hinders the development of cost-effective 3D integration in semiconductor manufacturing.
Innovation Solution
The development of a method to fabricate BEOL-compatible oxide semiconductor thin-film transistors using standard BEOL processing steps, incorporating a thin film transistor structure with a gate metal, gate dielectric, semiconductor layer, interlayer dielectric, and source/drain structure, where the liner structure is designed to accommodate the source/drain metal and prevent hydrogen diffusion, enabling integration within the interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current methods are used to fabricate 3D semiconductor devices, then device integration is achieved, but fabrication cost increases and manufacturing efficiency decreases
Solution Approach 1:
The patent applies universality by making the thin film transistor structure compatible with both front-end-of-line (FEOL) and back-end-of-line (BEOL) manufacturing processes. The transistor is designed to be formed using standard BEOL processing steps that can be integrated into existing 3D semiconductor fabrication workflows, allowing the same manufacturing infrastructure to handle multiple device types without requiring separate specialized processes, thereby improving productivity while controlling costs
2Ease of manufacture
If standard BEOL processing steps are used to fabricate thin film transistors, then fabrication cost decreases and manufacturing simplicity increases, but device performance and reliability may be compromised
Solution Approach 1:
The patent applies parameter changes by carefully selecting and optimizing the physical and chemical parameters of the materials used in the thin film transistor. The gate dielectric layer uses materials with specific dielectric constants and thickness ranges, the semiconductor layer uses oxide semiconductors with particular bandgap properties, and the source/drain metals are chosen for their conductivity and compatibility with BEOL processing temperatures. These parameter optimizations ensure that devices fabricated with standard BEOL processes achieve the required performance and reliability specifications
3Device complexity
If a simple liner structure is used to accommodate source/drain metal, then manufacturing complexity decreases, but hydrogen diffusion prevention capability is reduced
Solution Approach 1:
The patent applies composite materials by designing a multi-layer liner structure consisting of different material layers, each with specific properties. The liner structure includes a first liner layer and a second liner layer with different compositions and functions. This composite structure provides effective hydrogen diffusion barriers while maintaining compatibility with the source/drain metal and semiconductor layer, achieving protection against harmful hydrogen diffusion without requiring overly complex structural designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication of 3D semiconductor devices, reduces costs, and enhances the integration of thin film transistors within BEOL wiring levels, facilitating more efficient 3D integration while maintaining device performance.
Implementation Method 1
a gate dielectric layer disposed on the gate metal
Implementation Method 2
a first liner disposed between the interlayer dielectric and the source/drain metal... a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer
Data Source
AI summary
A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.