Metal Oxide TFT Array Crystallization at Lower Annealing Temperature
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Solution Overview
Problem
The high crystallization temperature of commonly used metal oxide semiconductor layers, typically above 600° C, poses a challenge in manufacturing thin film transistor array substrates for high-end display products, as it is difficult to meet the requirements for mobility and stability.
Innovation Solution
A method involving the formation of dispersed metal oxide grains on a substrate, followed by the deposition of an amorphous metal oxide semiconductor layer with matching metal elements, and subsequent annealing at a lower temperature to induce crystallization, reducing the crystallization temperature and improving transistor stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal oxide semiconductor layer is crystallized at high temperature (600°C or more), then the mobility and stability of thin film transistor are improved, but the manufacturing cost and process complexity increase
Solution Approach 1:
Metal oxide grains are formed on the substrate before depositing the amorphous metal oxide semiconductor layer. These pre-formed grains serve as crystal nuclei that guide and facilitate the crystallization process during annealing, enabling crystallization at lower temperatures (below 600°C) while still achieving the desired mobility and stability of the thin film transistor
Solution Approach 2:
The metal oxide grains act as an intermediary between the substrate and the amorphous metal oxide semiconductor layer. During the annealing process, these grains mediate the crystallization of the amorphous layer by providing nucleation sites, thereby reducing the energy barrier for crystallization and enabling the process to occur at lower temperatures
2Reliability
If metal oxide semiconductor layer is crystallized at high temperature (600°C or more), then the mobility of thin film transistor is improved, but the manufacturing complexity and difficulty increase
Solution Approach 1:
Metal oxide grains are formed on the substrate before depositing the amorphous metal oxide semiconductor layer. These pre-formed grains serve as crystal nuclei that guide and facilitate the crystallization process during annealing, enabling crystallization at lower temperatures (below 600°C) while still achieving the desired mobility and stability of the thin film transistor
Solution Approach 2:
The invention changes the physical and chemical parameters of the semiconductor layer by incorporating metal oxide grains with specific crystal structures and compositions. This modification alters the crystallization behavior of the amorphous metal oxide semiconductor layer, enabling it to crystallize at lower temperatures with improved mobility characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively lowers the crystallization temperature, enhances the stability of metal oxide thin film transistors, and facilitates mass production of high-end display panels by utilizing metal oxide thin film transistors.
Implementation Method 1
perform an annealing process on the amorphous metal oxide semiconductor layer, to obtain a crystallized metal oxide semiconductor layer
Implementation Method 2
perform an annealing process on the amorphous metal oxide semiconductor layer
Data Source
AI summary
The present disclosure provides a method for manufacturing a thin film transistor array substrate and a display panel. The method includes: forming a plurality of dispersed metal oxide grains on a substrate; forming an amorphous metal oxide semiconductor layer in contact with the plurality of metal oxide grains, and at least one metal element in the metal oxide grain is same as metal elements in the metal oxide semiconductor layer; performing an annealing process on the amorphous metal oxide semiconductor layer, to obtain a crystallized metal oxide semiconductor layer.