Oxide Semiconductor TFT Layout With Fewer Mask Processes
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Solution Overview
Problem
The increasing number of mask processes in the fabrication of transistor array substrates leads to higher fabrication costs and decreased yield, compromising the reliability and uniformity of thin-film transistors.
Innovation Solution
A thin-film transistor design that reduces the number of mask processes by using an active layer with oxide semiconductor crystals, integrated gap areas, and a conductive electrode layer composed of titanium, a metal layer with lower resistance, and indium tin oxide, allowing for reliable and uniform current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the number of mask processes is increased to fabricate thin-film transistors with reliable current characteristics, then the manufacturing precision and reliability improve, but the fabrication cost increases and yield decreases
Solution Approach 1:
The gate electrode, source electrode, and drain electrode are formed as a single integrated conductive layer rather than separate layers requiring individual mask processes. This merging of electrode structures reduces the number of mask processes from three to one, thereby improving fabrication yield while maintaining the precise geometric relationships needed for reliable current characteristics through single-step patterning
2Productivity
If the number of mask processes is reduced to improve fabrication yield, then productivity increases, but the manufacturing precision and reliability of current characteristics deteriorate
Solution Approach 1:
By combining the gate, source, and drain electrodes into a single conductive layer formed in one mask process, the invention achieves high fabrication yield while maintaining manufacturing precision. The single patterning step ensures uniform electrode dimensions and precise relative positioning, which are critical for consistent current characteristics across all transistors
3Manufacturing precision
If multiple mask processes are used to fabricate separate electrode layers, then the structural precision of individual electrodes improves, but the fabrication cost increases
Solution Approach 1:
The invention merges the gate, source, and drain electrodes into a single conductive layer that is patterned in one mask process. This approach maintains the necessary geometric precision of individual electrodes through single-step patterning while significantly reducing fabrication cost by eliminating two mask processes and associated alignment and processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method enables the fabrication of thin-film transistors with high reliability and uniformity of current characteristics using fewer mask processes, reducing fabrication costs while maintaining performance.
Implementation Method 1
the active layer includes an oxide semiconductor including crystals
Implementation Method 2
a heat treatment process
Data Source
AI summary
A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.