Oxide Semiconductor TFT Panel Mask Reduction via Layer Merging
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Solution Overview
Problem
The manufacturing of TFT array panels using oxide semiconductors is costly and complex due to the damage caused by exposure to the atmosphere and dry etching, requiring additional etching prevention layers and multiple masks, which increases costs and complicates the process.
Innovation Solution
A TFT array panel design that includes a barrier layer on the insulating substrate, a dual-layer structure for the source and drain electrodes, and a passivation layer that acts as both a gate insulating layer and protection for the oxide semiconductor, allowing for the simultaneous formation of the gate and pixel electrodes in the same layer without the need for additional etching stop layers, reducing the number of masks and manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching prevention layer is formed on the oxide semiconductor layer to reduce damage, then the reliability of the oxide semiconductor is improved, but the device complexity and manufacturing cost increase due to additional masks and layers
Solution Approach 1:
The patent combines the gate insulating layer and passivation layer into a single integrated structure formed from one photosensitive thin film layer. This merged layer serves both as the gate insulator and as protection for the oxide semiconductor, eliminating the need for a separate etching prevention layer and reducing the total number of masks required in the manufacturing process.
Solution Approach 2:
The passivation layer is designed to perform multiple functions simultaneously: it acts as a protective barrier for the oxide semiconductor against etching damage, serves as the gate insulating layer, and provides planarization for subsequent electrode formation. This multi-functional design eliminates the need for separate dedicated protection layers.
2Manufacturing precision
If multiple masks are used to form different layers with precise patterns, then the manufacturing precision is improved, but the manufacturing cost increases
Solution Approach 1:
The patent forms both the gate insulating layer and passivation layer from a single photosensitive thin film using one exposure and development process. This combining of layers into one manufacturing step reduces the number of masks required while maintaining precise pattern formation through the photosensitive material's inherent resolution capabilities.
Solution Approach 2:
The single photosensitive layer serves dual purposes as both gate insulator and passivation layer, allowing one mask to define both functional regions. This universal approach maintains manufacturing precision while significantly reducing the total mask count and associated costs.
3Ease of manufacture
If the oxide semiconductor is exposed to the atmosphere during manufacturing, then the manufacturing process is simplified, but the channel part is damaged by steam causing TFT characteristic degradation
Solution Approach 1:
The patent forms the gate insulating layer and passivation layer to completely cover the oxide semiconductor layer before subsequent manufacturing steps. This preliminary protective action prevents atmospheric exposure and steam damage to the channel part during electrode formation and other processing steps, maintaining TFT characteristics without complicating the overall process.
Data Source
AI summary
A thin film transistor array panel includes a source electrode and a drain electrode on an insulating substrate, an oxide semiconductor on the insulating substrate and overlapping the source electrode and the drain electrode, a passivation layer overlapping the oxide semiconductor and on the insulating substrate, a gate electrode on the passivation layer, and a pixel electrode connected to the drain electrode. The gate electrode and the pixel electrode include a same material. The oxide semiconductor is between the source electrode and the gate electrode, and between the drain electrode and the gate electrode in a cross-sectional view of the thin film transistor array panel.