Oxide Semiconductor TFT Non-Overlapping Electrodes
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Solution Overview
Problem
Thin film transistors using oxide semiconductors face challenges such as deterioration of the active layer during gate insulating layer patterning and parasitic capacitance between source, drain, and gate electrodes, leading to signal delay and cross talk in active matrix flat panel display devices.
Innovation Solution
A thin film transistor design featuring a substrate with an oxide semiconductor active layer, a high etching selectivity dielectric gate insulating layer, and non-overlapping source and drain electrodes, allowing for low-temperature manufacturing without ion implantation and minimizing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If oxide semiconductor is used as active layer, then low-temperature manufacturing is enabled, but active layer deterioration occurs during gate insulating layer patterning
Solution Approach 1:
A protective layer is introduced as an intermediary between the oxide semiconductor active layer and the etching chemicals used during gate insulating layer patterning. This protective layer prevents direct contact between the etchant and active layer, thereby preventing active layer deterioration while maintaining the low-temperature manufacturing advantage of oxide semiconductors
2Device complexity
If source and drain electrodes are overlapped with gate electrode, then device integration is achieved, but parasitic capacitance increases causing signal delay and cross talk
Solution Approach 1:
The patent resolves the contradiction by transitioning from a two-dimensional overlapping layout to a three-dimensional stacked architecture. Source and drain electrodes are positioned in different vertical layers relative to the gate electrode, eliminating parasitic capacitance while maintaining device integration through vertical stacking rather than horizontal overlap
3Ease of manufacture
If conventional etching is used for gate insulating layer patterning, then manufacturing process is simplified, but active layer is deteriorated due to low etching selectivity
Solution Approach 1:
The protective layer serves as a mediator that enables the use of conventional etching processes without damaging the active layer. It provides the necessary etching selectivity barrier, allowing simplified manufacturing processes to be used while simultaneously protecting the active layer from deterioration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution prevents active layer deterioration and reduces parasitic capacitance, enabling faster signal transmission and higher image quality in flat panel displays without the need for additional equipment or processes.
Implementation Method 1
a gate insulating layer formed of a dielectric on the active layer, the dielectric having an etching selectivity of 20 to 100:1 with respect to the oxide semiconductor
Implementation Method 2
an active layer of an oxide semiconductor formed on the substrate
Implementation Method 3
a gate insulating layer formed of a dielectric on the active layer
Data Source
AI summary
A thin film transistor using an oxide semiconductor as an active layer, and its method of manufacture. The thin film transistor includes: a substrate; an active layer formed of an oxide semiconductor; a gate insulating layer formed of a dielectric on the active layer, the dielectric having an etching selectivity of 20 to 100:1 with respect to the oxide semiconductor; a gate electrode formed on the gate insulating layer; an insulating layer formed on the substrate including the gate electrode and having contact holes to expose the active layer; and source and drain electrodes connected to the active layer through the contact holes. Since the source and drain electrodes are not overlapped with the gate electrode, parasitic capacitance between the source and drain electrodes and the gate electrode is minimized. Since the gate insulating layer is formed of dielectric having a high etching selectivity with respect to oxide semiconductor, the active layer is not deteriorated.