Oxide Semiconductor TFT Structure With Offset Region for Stable Mobility
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Solution Overview
Problem
Thin film transistors (TFTs) face limitations in manufacturing due to issues such as high manufacturing costs, temperature requirements, and uniformity challenges, particularly in large-area display applications, and there is a need for improved electrical stability and mobility.
Innovation Solution
A thin film transistor design that includes a conductivity-providing part formed through doping without patterning the gate insulation layer, with an active layer featuring an offset part between the channel and conductivity-providing parts to minimize the influence of insulation layers and ensure effective channel width, using a method that adjusts the size of the photoresist pattern to form the offset between these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If poly-Si TFTs are manufactured by depositing and crystallizing a-Si to achieve high electron mobility and good stability, then the manufacturing cost increases due to additional crystallization processes and high process temperature requirements
Solution Approach 1:
The patent changes the material parameter from poly-Si to oxide semiconductor, which inherently provides high electron mobility without requiring high-temperature crystallization processes. This parameter change allows achieving the desired electrical performance while simplifying the manufacturing process and reducing costs.
Solution Approach 2:
The patent employs a-si TFT structure with oxide semiconductor active layer that can be manufactured using lower-cost processes compared to poly-Si TFTs. The design accepts the trade-off of using simpler manufacturing techniques while maintaining adequate performance through optimized device structure.
2Ease of manufacture
If oxide semiconductor TFTs are manufactured to achieve high mobility and low manufacturing cost, then the stability and electron mobility are lower than those of poly-Si TFTs
Solution Approach 1:
The patent uses a composite structure combining oxide semiconductor material with specific device architecture elements (gate insulation layer configuration, offset part design). This composite approach leverages the low-cost manufacturing advantage of oxide semiconductors while using structural optimizations to enhance stability and mobility to levels comparable with or exceeding poly-Si TFTs.
Solution Approach 2:
The patent applies local quality optimization by creating an offset part in the active layer that is not covered by the gate insulation layer. This localized structural modification improves carrier transport and reduces the influence of insulation layers, thereby enhancing electron mobility and stability in critical regions of the device.
3Reliability
If an offset part is introduced in the active layer to minimize the influence of insulation layers, then the device complexity increases
Solution Approach 1:
The patent segments the active layer into distinct functional regions: a channel part covered by the gate insulation layer and an offset part that is not covered. This segmentation allows the offset part to serve as a buffer region that minimizes the influence of the insulation layer on carrier transport, thereby improving electrical stability without requiring complex additional components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical stability, prevents leakage currents, and maintains threshold voltage stability, allowing for efficient and cost-effective manufacturing of TFTs suitable for large-area displays.
Implementation Method 1
a gate insulation layer between the active layer and the gate electrode, wherein the gate insulation layer covers a whole top surface of the active layer
Implementation Method 2
the conductivity-providing part is doped with a dopant
Data Source
AI summary
An embodiment of the present disclosure provides a thin film transistor, a method of manufacturing the thin film transistor and a display apparatus including the thin film transistor. The thin film transistor includes an active layer on a substrate, a gate electrode disposed apart from the active layer to at least partially overlap the active layer, and a gate insulation layer between the active layer and the gate electrode. The gate insulation layer can cover an entire top surface of the active layer facing the gate electrode. The active layer can include a channel part overlapping the gate electrode, a conductivity-providing part which does not overlap the gate electrode, and an offset part between the channel part and the conductivity-providing part. The offset part may not overlap the gate electrode, and the conductivity-providing part can be doped with a dopant.