Oxide TFT Buffer Layer for Low-Resistance Ohmic Contacts

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Solution Overview

Problem

Thin film transistors with oxide semiconductor films face challenges in achieving high-speed operation and reliability due to increased contact resistance and capacitance between metal electrodes and the oxide semiconductor film, leading to signal delay and variation in electric properties, which affects display devices like liquid crystal and light-emitting displays.

Innovation Solution

An inverted staggered thin film transistor structure is implemented with an oxide semiconductor film containing indium, gallium, and zinc, using a buffer layer with higher carrier concentration than the semiconductor layer to reduce contact resistance and enhance ohmic contact, and a titanium film is used for the electrodes to minimize resistance and hillock formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a low resistance metal material is used for source and drain electrodes to reduce wiring resistance, then signal delay is reduced, but contact resistance between the metal electrode and oxide semiconductor film increases due to Schottky junction formation

Engineering Contradiction:
Improvesignal transmission speedVSAvoidcontact resistance
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

An n-type buffer layer is introduced as an intermediary between the metal electrode and the oxide semiconductor film. This buffer layer has higher carrier concentration than the semiconductor layer, which reduces contact resistance and prevents Schottky junction formation, thereby maintaining reliable electrical contact while using low-resistance metal materials for the electrodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The carrier concentration parameter is changed by introducing an n-type buffer layer with higher carrier concentration than the semiconductor layer. This parameter change reduces the contact resistance at the electrode-semiconductor interface, allowing the use of low-resistance metal materials without suffering from Schottky junction effects.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If direct contact between source and drain electrodes and oxide semiconductor film is formed to simplify the structure, then manufacturing process is simplified, but capacitance increases which degrades frequency characteristics and hinders high speed operation

Engineering Contradiction:
Improvestructural simplicityVSAvoidfrequency characteristics
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The n-type buffer layer serves as an intermediary that reduces the capacitance between the source and drain electrodes and the oxide semiconductor film. By positioning this buffer layer between the electrodes and the semiconductor film, the parasitic capacitance is minimized, improving frequency characteristics and enabling high-speed operation while maintaining a relatively simple structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If oxide semiconductor film with uniform composition is used to reduce manufacturing complexity, then variation in electric properties increases due to sensitivity to contact conditions and capacitance effects

Engineering Contradiction:
Improvefilm composition uniformityVSAvoidelectric property variation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The oxide semiconductor structure is divided into regions with different carrier concentrations: a semiconductor layer with lower carrier concentration and n-type buffer layers with higher carrier concentration at the electrode interfaces. This local quality differentiation reduces sensitivity to contact conditions and capacitance effects, thereby reducing variation in electric properties while maintaining relatively simple film composition.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240413167A1Semiconductor device and method for manufacturing the same
Publication Date: 2024.12.12 SEMICON ENERGY LAB CO LTD
  • US20240413167A1 patent drawing
  • US20240413167A1 patent drawing
  • US20240413167A1 patent drawing

AI summary

An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.