Display Pixel Circuit Layout With Overlap-Controlled Oxide TFT Routing
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Solution Overview
Problem
Existing display devices face challenges in achieving improved display quality, particularly in the integration and layout of pixel circuits and connecting lines, which can lead to inefficiencies and reduced performance.
Innovation Solution
The display device incorporates a base layer with defined display and non-display regions, a circuit layer with pixel circuits and connecting lines, and an element layer, utilizing oxide semiconductor patterns and transistors with specific overlapping and non-overlapping configurations to enhance connectivity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pixel circuits and connecting lines are integrated in conventional layouts, then device complexity is reduced, but display quality and performance deteriorate
Solution Approach 1:
The patent transitions from planar 2D layout to 3D stacked architecture by placing pixel circuits, connecting lines, and light emitting elements in different vertical layers. The circuit layer contains transistors and connecting lines, while the element layer contains light emitting elements positioned above specific regions, enabling spatial separation that improves display quality without increasing lateral complexity
Solution Approach 2:
The display device is segmented into distinct functional layers: base layer, circuit layer, and element layer. Each layer performs specific functions - the circuit layer handles signal routing and pixel control, while the element layer handles light emission. This segmentation allows optimization of each layer independently, improving overall display quality without proportionally increasing device complexity
2Reliability
If connecting lines overlap with semiconductor patterns, then connectivity is improved, but parasitic effects increase
Solution Approach 1:
An insulating layer is introduced as an intermediary between the connecting lines and oxide semiconductor patterns. This insulating layer allows the connecting lines to be positioned above the semiconductor patterns for reliable connectivity while preventing direct electrical contact that would create parasitic effects, thus mediating between the conflicting requirements
Solution Approach 2:
The connecting lines are moved from the same plane as semiconductor patterns to a higher vertical dimension. By positioning connecting lines above the oxide semiconductor patterns in the circuit layer, the patent achieves spatial separation that reduces parasitic effects while maintaining connectivity through vertical alignment and electrical connection at specific contact points
Data Source
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AI summary
A display device includes: a base layer including a display region and a non-display region in the base layer; a circuit layer on the base layer; and an element layer on the circuit layer, and including a light emitting element, wherein the circuit layer includes: a pixel circuit connected to the light emitting element; a data line connected to the pixel circuit; a vertical connecting line spaced apart from the data line in a first direction, and extending in a second direction; and a horizontal connecting line connecting the vertical connecting line to the data line in the display region, and extending in the first direction, wherein the pixel circuit includes a transistor including an oxide semiconductor pattern, wherein the horizontal connecting line includes an overlap part overlapping with a connecting pattern extending from the oxide semiconductor pattern, and wherein the transistor includes a gate overlapping with the overlap part.