Oxide TFT Array Panel Layout With Half-Tone Mask Processing
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Solution Overview
Problem
Current transistor manufacturing processes are limited by high costs and complexity due to the need for crystallization of polysilicon, which results in low charge mobility and high manufacturing costs, while amorphous silicon has low charge mobility, making it difficult to produce high-performance transistors.
Innovation Solution
A transistor display panel design that includes a substrate with a first transistor having a semiconductor, a multi-layer gate electrode, and connecting members, where the gate electrode and connecting members are formed using a half-tone mask to reduce the number of manufacturing processes and time, thereby lowering costs and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon is used to achieve high charge mobility, then transistor performance is improved, but manufacturing cost increases and process complexity increases due to crystallization requirements
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor, fundamentally altering the semiconductor's physical and chemical properties. This enables achieving high charge mobility without requiring complex crystallization processes, as oxide semiconductors can be deposited in amorphous form and still provide superior electrical characteristics
Solution Approach 2:
The patent employs a simpler, more cost-effective oxide semiconductor material that can be processed using conventional low-cost deposition techniques rather than expensive polysilicon crystallization equipment. This substitutes expensive, complex manufacturing with cheaper, simpler processes while maintaining or improving performance
2Reliability
If polysilicon crystallization process is used, then charge mobility is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the semiconductor material from polysilicon to oxide semiconductor, fundamentally altering the material parameters. This enables achieving high charge mobility through simple deposition processes rather than expensive crystallization, as oxide semiconductors inherently provide high mobility in amorphous form
Solution Approach 2:
The patent substitutes expensive polysilicon crystallization processes with cheaper oxide semiconductor deposition. The oxide semiconductor can be deposited using conventional, low-cost techniques such as sputtering or evaporation, eliminating the need for expensive crystallization equipment and reducing manufacturing costs
3Ease of manufacture
If amorphous silicon is used for simple manufacturing, then manufacturing cost is reduced, but charge mobility is limited and transistor performance deteriorates
Solution Approach 1:
The patent changes the semiconductor material from amorphous silicon to oxide semiconductor, fundamentally altering the material parameters. This enables achieving both manufacturing simplicity and high charge mobility, as oxide semiconductors can be deposited in amorphous form using simple processes while inherently providing superior electrical characteristics compared to amorphous silicon
Solution Approach 2:
The patent uses oxide semiconductor materials that combine the manufacturing simplicity of amorphous materials with the high charge mobility typically associated with crystalline materials. The oxide semiconductor structure provides a composite benefit of easy deposition processes while achieving high-performance electrical characteristics
Data Source
AI summary
A transistor display panel according to an exemplary embodiment includes: a substrate; a first transistor disposed on the substrate; and a pixel electrode connected to the first transistor, wherein the first transistor includes a lower electrode disposed on the substrate, a first semiconductor overlapping the lower electrode, a first insulating layer covering the first semiconductor, a first gate electrode disposed on the first insulating layer and overlapping the first semiconductor, and a first source connecting member and a first drain connecting member disposed on the same layer as the first gate electrode and connected to the first semiconductor, wherein the first gate electrode is formed as a triple layer, the first source connecting member and first drain connecting member are formed as a double layer, and the first source connecting member is connected to the lower electrode.