Oxide Semiconductor TFT Structure for Lower Wiring Parasitic Capacitance
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Solution Overview
Problem
In semiconductor devices, parasitic capacitance between wirings can lead to signal distortion, increased power consumption, and reduced display quality, especially in miniaturized circuits and active matrix display devices, where high operation speed and stable electric characteristics are required.
Innovation Solution
A semiconductor device structure is implemented with an oxide insulating layer covering the peripheral portion of the oxide semiconductor layer, reducing parasitic capacitance and enabling high-speed operation of thin film transistors, which includes a channel formation region overlapping with the gate electrode layer and an oxide insulating layer covering the periphery and side surfaces, thereby reducing signal distortion and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate wiring and source wiring intersect with each other in a semiconductor device, then the device can be manufactured with standard wiring layout, but parasitic capacitance is formed between the wirings causing signal distortion and increased power consumption
Solution Approach 1:
An insulating layer is introduced as an intermediary substance between the gate wiring and source wiring at their intersection point. This mediator reduces the parasitic capacitance formed between the two conductors by providing electrical isolation, thereby suppressing signal distortion and reducing power consumption while maintaining the standard wiring layout configuration
2Volume of moving object
If the distance between wirings is reduced to miniaturize the circuit, then the device size is reduced, but parasitic capacitance between the wirings is increased
Solution Approach 1:
An insulating layer is positioned between wirings that are closely spaced for miniaturization purposes. This intermediary insulating structure prevents excessive parasitic capacitance from developing between the adjacent wirings, enabling the circuit to be miniaturized without suffering from the harmful effects of increased parasitic capacitance
3Device complexity
If a large parasitic capacitance is formed between wirings, then the wiring structure can be simplified, but signal transmission is delayed and cross talk occurs
Solution Approach 1:
An insulating layer is introduced as a mediator between intersecting or adjacent wirings to reduce parasitic capacitance. This reduction in parasitic capacitance decreases the time constant for signal transmission, thereby reducing signal delay and preventing cross-talk between neighboring signal lines while keeping the wiring structure relatively simple
Data Source
AI summary
An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.