Oxide Semiconductor Thin Film Transistor Reducing Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Thin film transistors using silicon semiconductors face limitations in performance due to parasitic capacitance, which degrades characteristics and increases manufacturing time and cost, especially when using polysilicon, while amorphous silicon offers low charge mobility and high production costs.
Innovation Solution
A thin film transistor design incorporating an oxide semiconductor with a gate insulating layer and source/drain regions having higher carrier concentrations than the channel region, reducing parasitic capacitance and improving performance through specific manufacturing processes that include etch stoppers and plasma treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polysilicon is used to achieve high charge mobility, then charge mobility is improved, but manufacturing time and cost increase due to additional crystallization processes
Solution Approach 1:
The patent changes the material parameter from polysilicon to oxide semiconductor, which inherently provides high charge mobility without requiring crystallization processes. This material substitution resolves the contradiction by achieving high speed performance through different physical properties of the semiconductor material.
Data Source
AI summary
A thin film transistor array panel includes a substrate, a light blocking film disposed on the substrate, a buffer layer covering the light blocking film, and a channel region disposed on the buffer layer. A source region and a drain region are disposed in the same layer as the channel region. A gate insulating layer is disposed on the channel region, and a gate electrode overlaps the channel region, with the gate insulating layer interposed between the gate electrode and the channel region. A passivation layer is disposed on the gate electrode, the source region, the drain region, and the buffer layer. A source electrode and a drain electrode are disposed on the passivation layer, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than in the channel region.