Oxide Semiconductor TFT Pixel Electrode Layer Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing processes for liquid crystal display devices using oxide semiconductor TFTs with a top gate structure in FFS mode are complex and costly due to the need for multiple layers and complex electrode configurations.
Innovation Solution
The design includes a configuration where the pixel electrode is formed from the same oxide film as the semiconductor layer, with a connection electrode from a transparent conductive film connecting source wiring lines to the semiconductor layer, reducing the number of layers and simplifying the manufacturing process, and eliminating the need for a pixel contact hole.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a top gate structure oxide semiconductor TFT is used in FFS mode, then high current supply performance and space saving are achieved, but manufacturing process complexity and costs increase due to multiple layers and complex electrode configurations
Solution Approach 1:
The pixel electrode and common electrode are merged into a single transparent conductive film layer, forming both electrodes simultaneously through one deposition process. This eliminates the need for separate deposition steps and complex multilayer structures while maintaining the FFS mode functionality and top gate TFT performance.
Solution Approach 2:
The transparent conductive film serves multiple functions: it acts as both the pixel electrode and common electrode, provides light transmission, and enables electrical connections. This multi-functionality reduces the number of required layers and simplifies the manufacturing process while achieving the desired electrical performance.
2Reliability
If multiple layers of transparent electrodes and insulating layers are provided for FFS mode, then proper electrode configuration is achieved, but manufacturing processes increase and costs rise
Solution Approach 1:
Multiple electrode functions are combined into a single transparent conductive film layer, reducing the number of deposition steps from multiple separate electrode formations to one unified process. This maintains proper electrode configuration while significantly simplifying manufacturing.
Solution Approach 2:
Both pixel electrode and common electrode patterns are formed simultaneously in one deposition step, performing multiple electrode formation actions at once. This preliminary combined action eliminates subsequent separate electrode deposition steps and reduces overall process complexity.
3Reliability
If traditional multilayer electrode structures are used, then proper electrical isolation is achieved, but metal occupancy ratio increases and aperture ratio decreases
Solution Approach 1:
The transparent conductive film is selectively patterned to form electrode regions with different electrical potentials in different local areas. This local differentiation provides proper electrical isolation between pixel and common electrodes while maintaining high light transmission and maximizing aperture ratio through minimal metal occupancy.
Data Source
AI summary
An active matrix substrate of a liquid crystal display device includes a first substrate, a light blocking layer, a lower insulating layer, a pixel TFT, a source wiring line, a pixel electrode, and a common electrode. The pixel TFT includes an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, and first and second low-resistive regions. The source wiring line is located between the main surface of the first substrate and the lower insulating layer, and is formed from a conductive film the same as the light blocking layer. The pixel electrode is formed from an oxide film the same as the oxide semiconductor layer, and is continuous with the second low-resistive region. The active matrix substrate further includes a connection electrode that is formed from a transparent conductive film the same as the common electrode and connects the source wiring line to the first low-resistive region.


