Oxide TFT Vertical Structure Mask Reduction
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Solution Overview
Problem
The manufacturing process of oxide thin film transistors with a vertical structure is cumbersome due to the need for multiple mask processes, leading to poor ohmic contact and increased parasitic capacitance, which affects the display effect.
Innovation Solution
A method that forms a source electrode and insulation pattern on a substrate, followed by the formation of an active layer, gate electrode, and then a drain electrode through plasma treatment, reducing the number of mask processes and ensuring the drain electrode and active layer are made from the same material, eliminating dual-layer overlap and improving contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple mask processes are used to manufacture oxide thin film transistors with vertical structure, then the transistor characteristics are improved, but the manufacturing process becomes cumbersome and complex
Solution Approach 1:
The patent combines multiple mask processes into a single mask process by strategically designing the active layer pattern formation to simultaneously define the source, drain, and gate regions. This merging approach maintains the vertical structure TFT characteristics while significantly simplifying the manufacturing process complexity.
Solution Approach 2:
The active layer serves multiple functions: it acts as the semiconductor channel, defines the source and drain regions through its pattern, and establishes the gate structure boundaries. This multi-functionality eliminates the need for separate mask processes for each component, reducing overall process complexity while maintaining device performance.
2Manufacturing precision
If multiple mask processes are used to form source, drain and gate electrodes separately, then the electrode positioning precision is improved, but the production efficiency is reduced
Solution Approach 1:
The patent merges the formation of source, drain, and gate electrodes into a single patterning step by using the active layer pattern as a universal template. This approach maintains precise electrode positioning through careful pattern design while dramatically improving production efficiency by eliminating repeated mask and etch cycles.
Solution Approach 2:
The active layer is formed with a pre-designed pattern that anticipates the final electrode configurations. By preparing the active layer pattern in advance with the correct geometry, the subsequent electrode formation can proceed in a single step without requiring multiple positioning operations, thus maintaining precision while enhancing productivity.
3Shape
If the drain electrode is formed by separate mask process, then the electrode structure is well-defined, but the ohmic contact with active layer is poor and parasitic capacitance increases
Solution Approach 1:
The patent combines the drain electrode formation with the active layer patterning process, ensuring that the drain electrode is formed in direct contact with the active layer in the same processing step. This merging eliminates interface defects and ensures optimal ohmic contact while maintaining well-defined electrode structure through the pattern transfer process.
Solution Approach 2:
The patent uses the same material and formation process for both the active layer and drain electrode, ensuring material homogeneity at the interface. This homogeneity improves ohmic contact quality by eliminating material mismatches and interface defects that would otherwise increase parasitic capacitance, while the pattern transfer process maintains structural definition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Simplifies the manufacturing process, enhances ohmic contact, and reduces parasitic capacitance, thereby improving the display effect of thin film transistors.
Implementation Method 1
performing a plasma treatment to the exposed first portion of the active layer, thereby forming a drain electrode
Data Source
AI summary
A method for manufacturing a thin film transistor includes: forming a source electrode and a first insulation pattern, where an orthographic projection of the first insulation pattern at a substrate is within an orthographic projection of the source electrode at the substrate; forming an active layer, a second insulation pattern and a gate electrode on the substrate, an exposed portion of the source electrode not covered by the first insulation pattern and the first insulation pattern; exposing a first portion of the action layer on the first insulation pattern by removing parts of the gate electrode and the second insulation pattern; and performing a plasma treatment to the exposed first portion, thereby forming a drain electrode.