Oxide Nano-Sheet TFT Power Switches for Low-Area Semiconductor Logic
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Solution Overview
Problem
The challenge of minimizing power consumption in semiconductor devices while maintaining device size and density is exacerbated by the need for additional circuitry in existing power control technologies, which often require larger chip areas.
Innovation Solution
Implementing a power switch circuit at the BEOL circuit level using thin-film transistors (TFTs) with oxide semiconductor nano-sheets, such as IGZO, and a multiple stacked nano-sheet gate-all-around oxide semiconductor device structure to reduce device size and increase device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If additional circuitry is used for power control, then power consumption is reduced, but chip area increases
Solution Approach 1:
The patent implements power switch circuits by nesting TFT structures within existing BEOL interconnect layers. The TFTs are formed using the same metal layers (M1-M6) already present in the logic circuit, with power switches integrated into M1 and M2 layers. This nested approach allows power control functionality to be embedded within the existing chip structure without requiring additional dedicated circuit area.
Solution Approach 2:
The patent makes existing BEOL metal layers serve multiple functions: they simultaneously serve as interconnect wiring for logic circuits and as gate electrodes for TFT-based power switches. The M1 and M2 metal layers are used both for signal routing and for controlling power delivery to standard cells, eliminating the need for separate power control circuitry.
2Area of stationary object
If device size is minimized, then semiconductor device density increases, but power control capability is compromised
Solution Approach 1:
Power switch circuits are nested within the existing logic circuit interconnect structure. TFTs are formed using the same BEOL metal layers (M1-M6) that already exist in the device, with power switches specifically implemented in M1 and M2 layers. This allows full power control functionality to be integrated without increasing device footprint.
Solution Approach 2:
The patent transitions from planar power control to three-dimensional integration by forming TFT structures that utilize vertical stacking of metal layers. The gate-all-around TFT architecture wraps gate electrodes around channel regions in multiple layers, enabling power control functionality to be added in the vertical dimension rather than consuming horizontal chip area.
3Area of stationary object
If BEOL circuit level power switches are used, then device area is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the fabrication processes for logic circuits and power switch circuits into a single unified BEOL process flow. Both TFTs and logic circuits share the same metal layer deposition, patterning, and etching steps. The power switch TFTs are formed using the existing M1-M6 metal layers without requiring separate manufacturing equipment or process modules.
Solution Approach 2:
The existing BEOL interconnect structure serves dual purposes: it provides both the wiring infrastructure for logic circuits and the gate electrode structure for TFT power switches. The metal layers self-organize to fulfill both functions through appropriate patterning, eliminating the need for additional dedicated power control infrastructure.
4Loss of energy
If oxide semiconductor TFTs are used, then leakage current is reduced, but device fabrication difficulty increases
Solution Approach 1:
The fabrication process for oxide semiconductor TFTs is merged with the existing BEOL metal processing sequence. The same sputtering, annealing, and patterning tools used for logic circuit metal layers are employed to form TFT structures. Oxide semiconductor films are deposited and processed within the existing temperature and equipment constraints of the BEOL facility.
Solution Approach 2:
The patent optimizes processing parameters to enable oxide semiconductor TFT fabrication within standard BEOL conditions. Annealing temperatures, oxygen plasma treatment durations, and sputtering conditions are adjusted to achieve low leakage current performance while remaining compatible with existing manufacturing equipment capabilities and thermal budgets.
Data Source
AI summary
A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.