Oxide Semiconductor TFT Aperture Ratio via Reducing Layer
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Solution Overview
Problem
Current display devices face challenges in achieving high-definition and high-aperture-ratio displays at a lower cost, particularly due to the limitations of oxide semiconductor TFTs in maintaining a balance between device performance and manufacturing complexity.
Innovation Solution
A semiconductor device configuration featuring a substrate with a gate electrode, gate insulating layer, oxide layer with semiconductor and conductor regions, source and drain electrodes, and a transparent electrode, where the reducing insulating layer contacts the conductor region without affecting the channel region, allowing for a simpler manufacturing process and increased aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If oxide semiconductor TFTs are used to reduce TFT size and increase aperture ratio, then the aperture ratio is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines the formation of the oxide semiconductor layer and the reducing insulating layer into a single sputtering process step. By forming these layers simultaneously and then patterning them together using one photomask, the manufacturing process is simplified while still achieving the desired aperture ratio improvement through the reduced TFT size enabled by oxide semiconductor high mobility
Solution Approach 2:
The reducing insulating layer serves multiple functions: it reduces the oxide semiconductor in the contact region to create the conductor region, and it also serves as part of the pixel electrode structure. This multi-functionality reduces the number of separate manufacturing steps needed while maintaining the aperture ratio benefits
2Measurement precision
If the definition of liquid crystal display devices is increased, then the display quality is improved, but the pixel aperture ratio decreases
Solution Approach 1:
The patent changes the material parameter of the semiconductor layer from conventional materials to oxide semiconductor, which has higher carrier mobility. This parameter change allows the TFT to be made smaller for the same driving capability, thereby maintaining high aperture ratio even when display definition is increased
3Illumination intensity
If the aperture ratio of liquid crystal display devices is increased, then the display brightness is improved, but the power dissipation increases
Solution Approach 1:
By changing to oxide semiconductor material with higher mobility, the patent enables smaller TFT dimensions that occupy less pixel area. This increases the aperture ratio, allowing more light transmission for better brightness while the improved transistor efficiency reduces the power needed to drive the pixel, offsetting the increased backlight power requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the fabrication of a TFT substrate with a higher aperture ratio and definition, reducing manufacturing complexity and costs while maintaining the advantages of oxide semiconductor TFTs, such as higher mobility and lower power consumption.
Implementation Method 1
the reducing insulating layer has the property of reducing an oxide semiconductor included in the oxide layer
Data Source
AI summary
This semiconductor device (100A) includes: a gate electrode (3) formed on a substrate (2); a gate insulating layer (4) formed on the gate electrode; an oxide layer (50) which is formed on the gate insulating layer and which includes a semiconductor region (51) and a conductor region (55); source and drain electrodes (6s, 6d) electrically connected to the semiconductor region; a protective layer (11) formed on the source and drain electrodes; and a transparent electrode (9) formed on the protective layer. At least part of the transparent electrode overlaps with the conductor region with the protective layer interposed between them. The upper surface of the conductor region contacts with a reducing insulating layer (61) with the property of reducing an oxide semiconductor included in the oxide layer. The reducing insulating layer is out of contact with the channel region of the semiconductor region.