Oxide Semiconductor TFT Self-Aligned Electrode Formation
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Solution Overview
Problem
The manufacturing of thin film transistors (TFTs) for display devices is hindered by the need for multiple masking processes, which increases costs and time, particularly when forming polycrystalline silicon layers on large substrates, and existing semiconductors like amorphous silicon have low electron mobility.
Innovation Solution
A method for manufacturing a display substrate using a reduced number of masks, where a gate electrode and active pattern with an oxide semiconductor are formed, and a plasma treatment process is employed to self-align the source and drain electrodes without overlapping with the gate electrode, utilizing an etch stopper and photoresist patterns to promote reduction reactions and form electrodes with enhanced conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple masking processes are used to form source and drain electrodes, then manufacturing precision is improved, but manufacturing complexity and time increase
Solution Approach 1:
The source and drain electrodes are formed through a self-aligned process where the electrodes automatically position themselves relative to the gate electrode and active pattern without requiring additional masking steps. The electrode material is deposited to cover the entire substrate, and subsequent etching removes material based on the existing pattern structures, allowing the electrodes to self-align with the active regions.
Solution Approach 2:
The gate electrode and active pattern are formed first as preliminary structures that serve as alignment references for the subsequent source and drain electrode formation. These pre-formed structures guide the self-aligned electrode deposition and etching processes, eliminating the need for separate masking steps to define electrode positions.
2Reliability
If polycrystalline silicon is used for the active pattern, then electron mobility is improved, but manufacturing cost and process complexity increase due to crystallization requirements
Solution Approach 1:
The invention changes the material parameter from polycrystalline silicon to oxide semiconductor, which inherently provides high electron mobility without requiring high-temperature crystallization processes. This material substitution maintains the electrical performance benefits while eliminating the complex and costly crystallization steps needed for polycrystalline silicon formation.
3Ease of manufacture
If amorphous silicon is used for the active pattern, then manufacturing simplicity is maintained, but electron mobility and driving characteristics deteriorate
Solution Approach 1:
The invention changes the material composition from amorphous silicon to oxide semiconductor, which provides superior electron mobility while maintaining compatibility with low-temperature manufacturing processes. This parameter change in material composition achieves both high electrical performance and manufacturing simplicity without requiring complex crystallization procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and costs by self-aligning the source and drain electrodes, preventing misalignment, and achieving high electron mobility without the need for additional patterning processes, thereby improving the reliability and efficiency of the TFTs.
Implementation Method 1
A plasma treatment process is performed to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode
Implementation Method 2
forming the source electrode and the drain electrode may include implanting fluorine at upper portions of the active pattern
Data Source
AI summary
A method of manufacturing a display substrate includes forming a gate electrode on a base substrate, forming an active pattern which includes an oxide semiconductor and overlaps with the gate electrode, forming an etch stopper which partially covers the active pattern, and performing a plasma treatment process to promote a reduction reaction to portions of the active pattern exposed by the etch stopper, thereby forming a source electrode and a drain electrode.