Oxide Semiconductor TFT Self-Aligned Gate Mask
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Solution Overview
Problem
Thin film transistors in display devices face challenges with low electron mobility in amorphous silicon and high manufacturing costs for polycrystalline silicon, while oxide semiconductors offer high mobility but are prone to misalignment and reliability issues as channel length decreases.
Innovation Solution
A display substrate with a self-aligned channel region is manufactured using an oxide semiconductor active pattern, where a gate electrode is disposed on a base substrate, and insulation layers including aluminum oxide are formed to overlap the gate electrode, preventing misalignment and impurity diffusion, thereby improving reliability and operation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is decreased to improve operation speed and reduce power consumption, then operation speed and power consumption are improved, but process margins are degraded and reliability decreases due to increased misalignments
Solution Approach 1:
The gate electrode serves a dual function: as an electrical conductor and as a self-aligned mask for forming the insulation layer patterns. This self-service approach eliminates the need for separate alignment processes, ensuring precise positioning of the channel region even at reduced lengths, thereby maintaining reliability while enabling shorter channel dimensions for improved operation speed.
Solution Approach 2:
The gate electrode is formed first before the active pattern and insulation layers are created. This preliminary positioning establishes a reference structure that guides subsequent self-aligned formation processes, ensuring that the channel region maintains precise alignment and appropriate length dimensions even as overall device dimensions are scaled down.
2Reliability
If polycrystalline silicon is used to achieve high electron mobility, then electron mobility is improved, but manufacturing costs increase due to the crystallization process required
Solution Approach 1:
The invention changes the material parameter from polycrystalline silicon to oxide semiconductor, which inherently provides high electron mobility without requiring high-temperature crystallization processes. This parameter change enables achievement of high mobility characteristics while simplifying the manufacturing process and reducing costs.
3Ease of manufacture
If amorphous silicon is used for the semiconductor layer, then manufacturing is simpler, but electron mobility remains low resulting in poor driving characteristics
Solution Approach 1:
The invention changes the material parameter from amorphous silicon to oxide semiconductor, which provides significantly higher electron mobility while maintaining compatibility with low-temperature manufacturing processes. This parameter change resolves the contradiction by achieving both ease of manufacture and high electron mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the reliability and operation speed of thin film transistors by self-aligning the channel region and reducing parasitic capacitance, while maintaining a short channel length, thus addressing the limitations of existing technologies.
Implementation Method 1
Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide
Implementation Method 2
Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask
Data Source
AI summary
A display substrate and a method for manufacturing a display substrate are disclosed. In the method, a gate electrode is formed on a base substrate. An active pattern is formed using an oxide semiconductor. The active pattern partially overlaps the gate electrode. A first insulation layer pattern and a second insulation layer pattern are sequentially formed on the active pattern. The first insulation layer pattern and the second insulation layer pattern overlap the gate electrode. A third insulation layer is formed to cover the active pattern, the first insulation layer pattern and the second insulation layer pattern. Either the first insulation layer pattern or the second insulation layer pattern includes aluminum oxide. Forming the first insulation layer pattern and the second insulation layer pattern includes performing a backside exposure process using the gate electrode as an exposure mask.