Oxide Semiconductor TFT Structure for Self-Aligned OLED Pixels
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Solution Overview
Problem
Existing oxide semiconductor thin-film transistors (TFTs) in OLED display devices face challenges in achieving optimal performance characteristics for both switching and driving transistors, as they require different S-values for each function, and current manufacturing methods are inefficient and require multiple masks.
Innovation Solution
The design of oxide semiconductor TFTs with a lower amorphous layer and upper crystalline layer structure, allowing for self-aligned gate production, which enables the use of top-gate or bottom-gate electrodes to control channel resistance, and includes self-aligned source/drain regions, reducing the need for additional masks and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional oxide semiconductor TFT manufacturing methods are used, then transistors can be produced, but multiple masks are required leading to increased manufacturing complexity and reduced efficiency
Solution Approach 1:
The patent combines the gate electrode formation and source/drain region definition into a single masking step. The gate electrode pattern serves dual purposes: as the gate structure itself and as the mask for defining the source/drain regions, thereby merging two separate manufacturing steps into one and eliminating the need for additional masks
Solution Approach 2:
The gate electrode pattern is given multiple functions: it serves as the functional gate electrode for controlling the channel, and simultaneously acts as the mask pattern for defining the source/drain regions. This multi-functionality reduces the total number of masking steps required in the manufacturing process
2Reliability
If oxide semiconductor TFTs are used for both switching and driving functions, then low leakage current and high electron mobility are achieved, but different S-values are required for each function reducing performance optimization
Solution Approach 1:
The patent creates different local structures within the oxide semiconductor layer to achieve different electrical characteristics in different regions. By controlling the crystalline/amorphous phase distribution locally, the channel region can be optimized for switching performance while source/drain regions are optimized for driving function, allowing different S-values in different transistor types
Solution Approach 2:
The oxide semiconductor layer is segmented into distinct crystalline and amorphous regions with different functionalities. The channel region uses one phase composition optimized for charge transport, while source/drain regions use another phase composition optimized for contact properties, enabling independent optimization of different transistor functions
3Manufacturing precision
If top-gate or bottom-gate electrodes are used to control channel resistance, then self-aligned gate production is enabled, but additional manufacturing steps are required
Solution Approach 1:
The patent merges the gate electrode formation step with the source/drain region definition step by using the gate pattern itself as the mask. This eliminates the need for separate alignment steps and additional masks, achieving self-alignment without adding manufacturing complexity
Solution Approach 2:
The gate electrode pattern serves its own dual purpose: as the functional gate and as the alignment reference for source/drain regions. The structure is self-aligning by design, where the gate pattern automatically defines the position of source/drain regions without requiring external alignment marks or additional masking steps
Data Source
AI summary
An oxide semiconductor TFT device includes a substrate and a first oxide semiconductor TFT on the substrate. The first oxide semiconductor TFT includes a first oxide semiconductor layer, a first top-gate electrode, and a first source/drain electrode. The first oxide semiconductor layer includes a first channel region overlapping the first top-gate electrode, and two first low-resistive regions sandwiching the first channel region. The first source/drain electrode is located upper than the first top-gate electrode and extends through an insulating region overlapping one of the two first low-resistive regions to be in contact with the one of the two first low-resistive regions. Each of the two first low-resistive regions and the first channel region includes a lower amorphous layer and an upper crystalline layer having a composition identical to a composition of the amorphous layer.