Oxide TFT Array Substrate Layout With Shared Modulation Vias
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Solution Overview
Problem
Conventional pixel circuit designs for oxide TFTs require additional vias, occupying significant space and reducing the aperture opening ratio of display devices.
Innovation Solution
The array substrate design electrically connects modulation electrodes of multiple oxide thin film transistors as a modulation layer, connected to a gate electrode or source electrode through fewer vias than the number of transistors, reducing the number of vias and saving layout space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each oxide TFT is connected with individual vias to gate electrode or source electrode, then electrical connection is achieved, but the number of vias increases and layout space is occupied
Solution Approach 1:
The patent merges the connection paths of multiple oxide TFTs by introducing a shared via structure. Instead of providing individual vias for each TFT to connect to the gate electrode or source electrode, the invention combines multiple connection paths into a single via that serves multiple transistors simultaneously, thereby reducing the total number of vias and simplifying the device structure.
Solution Approach 2:
The shared via structure performs multiple functions: it provides electrical connection for multiple oxide TFTs simultaneously, acts as a common reference point for threshold voltage modulation, and reduces the overall via count in the pixel circuit. This multi-functional design optimizes the use of vias and improves the aperture ratio.
2Reliability
If additional vias are added for each oxide TFT, then electrical connection is ensured, but layout space is occupied and aperture opening ratio is reduced
Solution Approach 1:
The patent merges the connection paths of multiple oxide TFTs by introducing a shared via structure. Instead of providing individual vias for each TFT to connect to the gate electrode or source electrode, the invention combines multiple connection paths into a single via that serves multiple transistors simultaneously, thereby reducing the total number of vias and simplifying the device structure.
Solution Approach 2:
The patent optimizes the spatial arrangement of vias by transitioning from a distributed one-to-one via configuration to a shared via structure. This dimensional reorganization allows multiple TFTs to share a common via location, effectively reducing the horizontal and vertical space occupied by vias in the pixel circuit layout and increasing the aperture opening ratio.
3Area of stationary object
If modulation electrodes of multiple oxide TFTs are electrically connected as a modulation layer through fewer vias, then layout space is saved and aperture opening ratio is improved, but the connection structure becomes more complex
Solution Approach 1:
The shared via structure performs multiple functions: it provides electrical connection for multiple oxide TFTs simultaneously, acts as a common reference point for threshold voltage modulation, and reduces the overall via count in the pixel circuit. This multi-functional design optimizes the use of vias and improves the aperture ratio.
Solution Approach 2:
The patent segments the modulation electrodes of multiple oxide TFTs into a unified modulation layer that is selectively connected through shared vias. This segmentation allows independent control of different TFT groups while using a common connection infrastructure, balancing structural simplicity with functional flexibility.
Data Source
AI summary
The present application relates to an array substrate and a preparation method thereof, and a display device; wherein the array substrate comprises a substrate and a plurality of sub-pixels distributed in an array on the substrate, the sub-pixels comprising M oxide thin film transistors, each oxide thin film transistor comprising a modulation electrode, a gate electrode, a source electrode and a drain electrode arranged in a stack, wherein the modulation electrodes of the M oxide thin film transistors are electrically connected to each other as a modulation layer, and the modulation layer is electrically connected to the gate electrode through N first vias, wherein M and N are both integers, and N<M.