Oxide TFT Gate Insulator Layout for Short-Channel Stability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional thin film transistors using oxide semiconductors face challenges in channel length design due to shifting threshold voltage and increased variability, limiting their flexibility and reliability, especially when reducing size.
Innovation Solution
The semiconductor device incorporates a specific configuration with a polycrystalline oxide semiconductor layer, a gate insulating layer, and a metal oxide layer, including a non-overlapping region of the gate insulating layer to suppress hydrogen diffusion and form a Low-Doped Drain (LDD) region, which enhances carrier mobility and drain breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the channel length is reduced to decrease device size, then the device can be miniaturized, but the threshold voltage shifts and variability increases
Solution Approach 1:
The gate insulating layer is divided into a first gate insulating layer and a second gate insulating layer with different dielectric constants. The first layer (closer to channel) has higher dielectric constant than the second layer (closer to gate electrode), creating a segmented structure that optimizes electric field distribution and maintains threshold voltage stability even at reduced channel lengths.
Solution Approach 2:
Different regions of the gate insulating structure have different dielectric properties - the region closer to the channel uses high-k material for strong field effect, while the region closer to the gate electrode uses lower-k material to reduce parasitic capacitance and prevent threshold voltage shifts, achieving local optimization of electrical characteristics.
2Device complexity
If a conventional single-layer gate insulating structure is used, then the device structure is simple, but the field-effect mobility is limited and threshold voltage control is poor
Solution Approach 1:
The gate insulating layer employs a composite structure with two different insulating materials having different dielectric constants. This composite configuration enables simultaneous achievement of high field-effect mobility through enhanced electric field control and stable threshold voltage through optimized charge distribution, overcoming limitations of single-material structures.
Solution Approach 2:
The invention changes the dielectric constant parameter across the gate insulating layer thickness - using high-k material near the channel interface and lower-k material near the gate electrode. This parameter gradient optimizes the electric field distribution, improving carrier mobility while maintaining reliable threshold voltage control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration maintains high field-effect mobility and reliability even at short channel lengths, preventing threshold voltage shifts and improving electrical characteristics.
Implementation Method 1
a gate insulating layer on the oxide semiconductor layer... A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer
Implementation Method 2
an oxide semiconductor layer having a polycrystalline structure on the first insulating layer... The thin film transistor using an oxide semiconductor as a channel is known to have a higher field-effect mobility
Data Source
AI summary
A semiconductor device comprises a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a gate wiring on the gate insulating layer, and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. The first region overlaps the gate insulating layer and the gate wiring. The third region is in contact with the second insulating layer. A distance from a top surface of the second region to a top surface of the second insulating layer is longer than a distance from a top surface of the third region to the top surface of the second insulating layer.