Oxide Thin Film Transistor with Stacked Gate Structure
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Solution Overview
Problem
Current flat panel display devices using amorphous silicon thin film transistors face limitations in achieving high definition and high driving speed due to low mobility, while polycrystalline silicon transistors require high temperature processing and additional mask procedures for high density region formation, complicating the fabrication process.
Innovation Solution
A flat panel display device with an oxide thin film transistor and a simplified fabrication method that includes a buffer film, an oxide semiconductor layer, a gate insulation film, source and drain electrodes, and a pixel electrode, where the oxide semiconductor layer is formed at a larger width than the gate insulation film and gate electrode, allowing metallization without additional mask procedures and securing an effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If amorphous silicon thin film transistor is used, then lower temperature deposition is achieved, but electron mobility is reduced below 0.50 cm2/Vs
Solution Approach 1:
The patent changes the material parameter from conventional silicon to oxide semiconductor (IGZO), which fundamentally alters the deposition temperature-mobility relationship. IGZO enables high electron mobility (>10 cm2/Vs) to be achieved at low deposition temperatures (below 350°C), breaking the trade-off that exists for amorphous silicon where low temperature deposition results in mobility below 0.50 cm2/Vs
Solution Approach 2:
The patent employs a composite structure combining oxide semiconductor layer with specific gate insulation films (silicon oxide, silicon nitride, or silicon oxynitride). This composite material system enables simultaneous achievement of low deposition temperature and high electron mobility, as the oxide semiconductor provides high mobility while the gate insulation films provide appropriate dielectric properties for low-temperature processing
2Reliability
If polycrystalline silicon thin film transistor is used, then high electron mobility of several tens through hundreds cm2/Vs is achieved, but high temperature treatment above 1000° C. and additional mask procedures are required
Solution Approach 1:
The patent changes the material from polycrystalline silicon to oxide semiconductor, which allows high electron mobility (>10 cm2/Vs) to be achieved without high-temperature crystallization treatment. The oxide semiconductor can be deposited and processed at temperatures below 350°C, eliminating the need for 1000°C treatment while maintaining high mobility performance
Solution Approach 2:
The patent extracts and eliminates the unnecessary additional mask procedures required for forming high density regions in polycrystalline silicon. The oxide semiconductor's inherent properties allow source and drain regions to be formed directly during deposition without requiring separate mask steps, thereby simplifying the fabrication process and reducing device complexity
3Ease of manufacture
If oxide semiconductor layer is formed at larger width than gate insulation film and gate electrode, then metallization is simplified without additional mask procedures, but channel length control becomes critical
Solution Approach 1:
The patent performs preliminary patterning of the oxide semiconductor layer to form source and drain regions with appropriate width before gate electrode formation. This preliminary action ensures that when the gate electrode is subsequently formed with narrower width, the oxide semiconductor layer already has the correct configuration for direct metallization without requiring additional mask procedures, while maintaining precise channel length control
Data Source
AI summary
A flat panel display device with an oxide thin film transistor is disclosed which includes: an oxide semiconductor layer which has a width of a first length and is formed on a buffer film; a gate insulation film which has a width of a second length and is formed on the oxide semiconductor layer; a gate electrode which has a width of a third length and is formed on the gate insulation film; an interlayer insulation film formed on the entire surface of the substrate provided with the gate electrode; source and drain electrodes formed on the interlayer insulation film and connected to the oxide semiconductor layer; a pixel electrode formed on a passivation film and connected to the drain electrode. The first length is larger than the second length and the second length is larger than the third length.