Oxide TFT Structure Split for Parasitic Capacitance and Mobility
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Solution Overview
Problem
Current display devices face challenges in minimizing parasitic capacitance in pixel transistors, which affects image quality, and in enhancing carrier mobility in driving circuit transistors, leading to suboptimal operation characteristics and reliability.
Innovation Solution
The display device incorporates transistors with different structures in the display and non-display areas, where pixel transistors have a gate insulating layer covering the active layer to minimize parasitic capacitance, and driving circuit transistors have an etched gate insulating layer to increase carrier mobility, both using the same oxide semiconductor material for manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the gate insulating layer covers the active layer in pixel transistors, then parasitic capacitance is minimized, but carrier mobility is reduced
Solution Approach 1:
The patent applies different gate insulating layer configurations to different transistor types: pixel transistors have a gate insulating layer covering the active layer to minimize parasitic capacitance, while driving circuit transistors have an etched gate insulating layer to increase carrier mobility. This local differentiation resolves the contradiction by optimizing each transistor type for its specific functional requirements.
2Reliability
If different transistor structures are used in display and non-display areas, then performance is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent segments the transistor population into two groups (pixel transistors and driving circuit transistors) with different gate insulating layer configurations. This segmentation allows each group to have optimized performance characteristics while maintaining a relatively streamlined manufacturing process through selective etching steps.
Data Source
AI summary
A display device includes a pixel including a first transistor, and a driving circuit including a second transistor. The first transistor includes a first active layer including first source and drain regions apart from each other with a first channel region therebetween, a first gate insulating layer on the first active layer and covering the first channel, source and drain regions, and a first gate electrode on the first gate insulating layer and overlapping the first channel region. The second transistor includes a second active layer including second source and drain regions apart from each other with a second channel region therebetween, a second gate insulating layer on a part of the second active layer including the second channel region and exposing the second source and drain regions, and a second gate electrode disposed on the second gate insulating layer and overlapping the second channel region.