Oxide TFT Synapse Circuit for Linear, Low-Leakage Weight Updates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing synapse circuits face challenges with non-volatile memories like RRAM and PRAM in achieving consistent, linear, and symmetrical weight updates, and CMOS-based circuits suffer from poor data preservation due to leakage current, making them unsuitable for large-scale neural network learning and long-term inference.
Innovation Solution
A synapse circuit utilizing n-type oxide thin film transistors with an oxide semiconductor channel, incorporating a 3T1C unit configuration, including a capacitor and transistors for potentiation and depression operations, to enhance linearity, symmetry, and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory (RRAM/PRAM) is used for synapse, then data retention is improved, but weight update linearity and symmetry deteriorate
Solution Approach 1:
The patent changes the electrical parameters of the synapse circuit by using n-type oxide TFTs with specifically engineered channel width-to-length ratios (W/L) for potentiation and depression transistors. This parameter optimization enables linear and symmetrical weight updates while maintaining non-volatile data retention, resolving the contradiction between reliability and manufacturing precision.
2Manufacturing precision
If CMOS transistors and capacitors are used for synapse circuit, then weight update linearity is improved, but data preservation ability deteriorates due to leakage current
Solution Approach 1:
The patent transitions from standard CMOS transistors to n-type oxide TFTs, changing the fundamental electrical parameters including threshold voltage and leakage characteristics. The oxide semiconductor material provides ultra-low leakage current while maintaining linear transistor operation, simultaneously improving data preservation and weight update linearity.
Solution Approach 2:
The patent uses composite material structures including n-type oxide semiconductor channels combined with specific dielectric materials (e.g., HfO2, Al2O3) and metal electrodes. This composite approach enables both low leakage current for data preservation and controlled linear characteristics for accurate weight updates.
3Productivity
If existing synapse circuits are used for large-scale neural network learning, then processing capability is improved, but accuracy during long-term inference deteriorates
Solution Approach 1:
The patent optimizes circuit parameters including transistor W/L ratios, capacitor sizes, and voltage levels to enable accurate long-term weight storage. The n-type oxide TFT parameters are specifically tuned to maintain weight precision over extended learning and inference periods, ensuring high accuracy in large-scale neural networks.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Synapse circuits, operating methods thereof, and neuromorphic devices including a synapse circuit are disclosed. A disclosed synapse circuit may include a capacitor comprising a first electrode, a second electrode, and a dielectric layer between them, wherein the first electrode is connected to a voltage source capable of applying a positive (+) voltage, a potentiation transistor having a first source connected to the second electrode, a first drain connected to a first power source, and a first gate for applying a first control signal, a depression transistor having a second drain connected to the second electrode, a second source connected to a second power source, and a second gate for applying a second control signal, and a read transistor having a third gate connected to the second electrode, a third source connected to a word line, and a third drain connected to a bit line. The potentiation transistor, the depression transistor, and the read transistor may be n-type oxide thin film transistors including an oxide semiconductor channel. The synapse circuit may have a 3-transistor 1-capacitor (3T1C) unit circuit configuration consisting of the potentiation transistor, the depression transistor, the read transistor, and the capacitor.