Oxide Semiconductor TFT with Self-Align Top Gate
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Solution Overview
Problem
Conventional thin film transistors (TFTs) face challenges such as low charge mobility, increased parasitic capacitance due to bottom gate structures, and complex manufacturing processes for polycrystal silicon TFTs, which limit device speed and scalability, and degrade image quality in large-sized display devices.
Innovation Solution
A semiconductor device with a thin film transistor (TFT) featuring plasma-treated source and drain regions with varying conductivities, a self-align top gate structure, and an oxide semiconductor channel layer that eliminates the need for crystallization and impurity doping, allowing for simplified manufacturing and improved charge mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon is used as the channel layer material, then the manufacturing process is simple, but the charge mobility is low (about 0.5 cm²/Vs)
Solution Approach 1:
The patent changes the material parameter from conventional amorphous silicon to oxide semiconductor (such as IGZO - indium gallium zinc oxide), which fundamentally alters the electrical properties while maintaining compatibility with existing TFT manufacturing processes. This material substitution enables higher charge mobility (exceeding 10 cm²/Vs) without requiring complex process changes, thus resolving the contradiction between manufacturing simplicity and charge mobility.
2Reliability
If polycrystal silicon is used as the channel layer material, then the charge mobility is improved, but the manufacturing process becomes more complicated and manufacturing cost increases
Solution Approach 1:
The patent employs oxide semiconductor material which inherently provides high charge mobility comparable to or exceeding polycrystal silicon, but without requiring the complex crystallization processes, impurity injection, and activation steps needed for polycrystal silicon. The oxide semiconductor can be deposited using simple sputtering or atomic layer deposition techniques, thus achieving high mobility while maintaining process simplicity.
Solution Approach 2:
The patent uses oxide semiconductor layers that can be formed through low-cost deposition techniques without requiring expensive high-temperature crystallization equipment or multiple complex processing steps. This approach provides a cost-effective alternative to polycrystal silicon while achieving comparable or superior electrical performance.
3Reliability
If polycrystal silicon layer is used as channel layer in large size display device, then the charge mobility is improved, but the image quality deteriorates due to irregular crystalline particle size
Solution Approach 1:
The patent switches to oxide semiconductor material which forms a uniform amorphous or nanocrystalline structure without the irregular large-grain crystallization issues of polycrystal silicon. This material provides consistent electrical properties across large substrate areas, ensuring uniform charge mobility and preventing image quality deterioration in large-sized display devices.
4Device complexity
If bottom gate structure is used, then the device structure is formed, but the parasitic capacitance increases which limits device speed
Solution Approach 1:
The patent inverts the conventional bottom gate structure to a top gate structure, where the gate electrode is positioned above the channel layer instead of below. This inversion reduces the overlap area between the gate electrode and source/drain regions, thereby minimizing parasitic capacitance and improving device switching speed while maintaining the essential field-effect transistor structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances operating speed, simplifies manufacturing, reduces costs, and maintains image quality across large display sizes by utilizing plasma-treated regions and oxide semiconductor layers, avoiding the limitations of amorphous and polycrystal silicon TFTs.
Implementation Method 1
The first source region and the first drain region may be plasma-treated
Data Source
Figure 1
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Figure 3A~3B
AI summary
Semiconductor devices including at least one thin film transistor (TFT) and methods of manufacturing the semiconductor devices. The semiconductor device may include an oxide TFT having a self-align top gate structure. The oxide TFT may include a first oxide semiconductor layer having a first source region, a first drain region, and a first channel region between the first source region and the first drain region, and a first gate insulating layer and a first gate electrode, which are sequentially stacked on the first channel region. A bottom gate electrode may be further disposed below the first oxide semiconductor layer, and the first oxide semiconductor layer may have a multilayer structure.