Oxide Semiconductor TFT with Oxygen Vacancy Reaction Layer
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Solution Overview
Problem
Conventional thin film transistors (TFTs) with oxide semiconductors face increased resistance and parasitic capacitance due to direct contact between source/drain electrodes and the active layer without an impurity layer, leading to suboptimal electrical characteristics.
Innovation Solution
A TFT design with a channel passivation layer and a reaction layer containing metal oxide, where low resistance patterns with oxygen vacancies are formed at the edges of the channel portion, reducing contact resistance and minimizing parasitic capacitance by allowing direct contact between source/drain electrodes and the oxide semiconductor pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If source electrode and drain electrode are in direct contact with oxide semiconductor active layer without impurity layer, then device structure is simplified, but contact resistance increases and parasitic capacitance is generated
Solution Approach 1:
The patent applies local quality by creating low resistance patterns at specific locations (edges of channel portion) rather than uniformly modifying the entire oxide semiconductor layer. This localized modification reduces contact resistance at electrode interfaces while preserving the high-quality oxide semiconductor in the channel region, thus resolving the contradiction between structural simplicity and electrical performance.
Solution Approach 2:
The patent changes the oxygen content parameter of the oxide semiconductor by forming oxygen vacancies through reaction with metal oxide. This parameter change creates regions with different electrical properties (low resistance patterns) within the oxide semiconductor layer, enabling direct electrode contact with acceptable contact resistance while maintaining the overall oxide semiconductor structure.
2Speed
If oxide semiconductor is used as active layer, then charge mobility is improved compared to amorphous silicon, but contact resistance increases due to lack of impurity layer
Solution Approach 1:
The patent creates local low resistance patterns at the edges of the channel portion where electrodes contact the oxide semiconductor. This localized modification provides low contact resistance pathways at interfaces while preserving the high-mobility oxide semiconductor properties in the channel region, thus resolving the contradiction between charge mobility and contact resistance.
Solution Approach 2:
The patent segments the oxide semiconductor layer into different functional regions: high-mobility channel portion and low-resistance contact portions. This segmentation is achieved by creating oxygen vacancies selectively at electrode contact regions, allowing each region to optimize its electrical properties for its specific function.
3Reliability
If oxide semiconductor is used as active layer, then uniform threshold voltage is achieved, but parasitic capacitance is generated between electrodes and gate electrode
Solution Approach 1:
The patent extracts or removes oxygen atoms from the oxide semiconductor at the edges of the channel portion to create oxygen vacancies. This extraction creates low resistance patterns that provide controlled contact pathways, reducing the harmful parasitic capacitance effect while preserving the uniform threshold voltage characteristics of the oxide semiconductor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical characteristics of TFTs by reducing contact resistance and minimizing parasitic capacitance, thereby improving charge mobility and operational efficiency.
Implementation Method 1
The reaction layer may further include oxygen atoms or oxygen ions transferred from the oxide semiconductor pattern
Data Source
AI summary
A thin film transistor includes a gate electrode on a substrate, a gate insulation layer which covers the gate electrode on the substrate, an oxide semiconductor pattern which is disposed on the gate insulation layer and includes a channel portion superimposed over the gate electrode, and low resistance patterns provided at edges of the channel portion, respectively, and including oxygen vacancies, a channel passivation layer on the oxide semiconductor pattern, a reaction layer which covers the oxide semiconductor pattern and the channel passivation layer, and includes a metal oxide, and a source electrode and a drain electrode which contact the oxide semiconductor pattern.