Oxide TFT Dielectric Stack for Warp-Resistant Display Substrates

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Solution Overview

Problem

Display devices face challenges in preventing substrate warpage, which affects display quality and energy consumption, despite advancements in thin-film transistors using polycrystalline silicon and oxide semiconductors.

Innovation Solution

Adjusting the composition ratio of nitrogen to silicon and layer density in the first lower interlayer dielectric layer, specifically forming it with silicon nitride and silicon oxide, to reduce compressive stress and maintain or improve oxide semiconductor transistor characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a conventional lower interlayer dielectric layer is used, then the manufacturing process is simple, but the substrate experiences warpage due to compressive stress

Engineering Contradiction:
Improvesubstrate flatnessVSAvoidinterlayer dielectric structure
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The lower interlayer dielectric layer is divided into two separate layers: a first lower interlayer dielectric layer (silicon nitride) and a second lower interlayer dielectric layer (silicon oxide). This segmentation allows each layer to have optimized properties - the silicon nitride layer provides structural support while the silicon oxide layer reduces compressive stress, preventing substrate warpage without excessive complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a composite structure combining silicon nitride and silicon oxide layers. The silicon nitride layer (first lower interlayer dielectric layer) provides mechanical strength, while the silicon oxide layer (second lower interlayer dielectric layer) has lower stress characteristics. This composite approach balances structural requirements with stress management to maintain substrate flatness

Inventive Principle:
Principle #40Composite materials

2Reliability

If the nitrogen to silicon composition ratio is not optimized, then the manufacturing process is simple, but the transistor characteristics deteriorate

Engineering Contradiction:
Improvetransistor characteristicsVSAvoidcomposition ratio control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent specifies optimizing the nitrogen to silicon composition ratio in the silicon nitride layer within a particular range (0.65 to 0.75). By controlling this compositional parameter, the layer density and stress characteristics are optimized to prevent hydrogen diffusion into the oxide semiconductor layer while maintaining good transistor characteristics such as threshold voltage and mobility

Inventive Principle:
Principle #35Parameter changes

3Strength

If the first lower interlayer dielectric layer has high layer density, then the structural strength is improved, but the compressive stress increases causing substrate warpage

Engineering Contradiction:
Improvestructural strengthVSAvoidcompressive stress
Core Design Contradiction:
StrengthVSStress or pressure

Solution Approach 1:

Different regions of the interlayer dielectric structure have different properties optimized for their specific functions. The first lower interlayer dielectric layer (silicon nitride) has higher layer density (2.4-2.6 g/cm³) for structural strength, while the second lower interlayer dielectric layer (silicon oxide) has lower density and lower stress. This local differentiation of material properties allows the structure to simultaneously achieve strength and stress management

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12108635B2Display device
Publication Date: 2024.10.01 SAMSUNG DISPLAY CO LTD
  • US12108635B2 patent drawing
  • US12108635B2 patent drawing
  • US12108635B2 patent drawing

AI summary

A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.