Oxide Semiconductor Top-Gate Transistor Layout for Low Signal Delay
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Solution Overview
Problem
Inverted staggered transistors used in display devices suffer from signal delay due to parasitic capacitance and occupy more area, degrading image quality, especially in large-sized or high-resolution displays, and lack stable semiconductor characteristics and high reliability.
Innovation Solution
A planar-type semiconductor device with oxide semiconductors is developed, featuring transistors with a top-gate structure and impurity elements like hydrogen, boron, or rare gases in regions not overlapping with gate, source, and drain electrodes, reducing parasitic resistance and increasing on-state current while maintaining low off-state current and small area occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an inverted staggered transistor is used, then the manufacturing process is simple and manufacturing cost is low, but signal delay increases due to parasitic capacitance and image quality degrades
Solution Approach 1:
The patent inverts the conventional transistor structure by placing the gate electrode on top of the semiconductor film instead of beneath it. This inversion changes the capacitance characteristics and reduces parasitic capacitance between the gate and source/drain electrodes, thereby reducing signal delay while maintaining manufacturing simplicity
2Ease of manufacture
If an inverted staggered transistor is used, then manufacturing cost is low, but occupation area increases
Solution Approach 1:
The patent utilizes vertical stacking in the top-gate structure, placing the gate electrode in the vertical dimension above the source and drain electrodes. This dimensional arrangement allows for more compact lateral spacing, reducing the overall occupation area while maintaining manufacturing cost effectiveness
3Area of moving object
If a planar transistor is used, then occupation area is reduced, but stable semiconductor characteristics and high reliability are not achieved
Solution Approach 1:
The patent introduces impurity elements selectively in specific regions of the semiconductor film, particularly in the channel region between source and drain electrodes. This localized modification of material composition enhances carrier concentration and improves semiconductor characteristics stability without increasing overall device area
4Power
If impurity elements are added to the oxide semiconductor film, then on-state current increases, but off-state current may increase
Solution Approach 1:
The patent carefully controls the spatial distribution of impurity elements, concentrating them in the channel region while avoiding excessive doping in other areas. This localized doping strategy enhances on-state current through improved carrier concentration in the active channel while minimizing off-state leakage current
Data Source
AI summary
A semiconductor device comprising an oxide semiconductor film, a gate electrode, a first insulating film, a source electrode, a drain electrode, and a second insulating film is provided. Each of a top surface of the gate electrode, a top surface of the source electrode, and a top surface of the drain electrode comprises a region in contact with the second insulating film. A top surface of the first insulating film comprises a region in contact with the gate electrode and a region in contact with the second insulating film and overlapping with the oxide semiconductor film in a cross-sectional view of the oxide semiconductor film. The oxide semiconductor film comprises a region in contact with the first insulating film and a region in contact with the second insulating film and adjacent to the region in contact with the first insulating film in the cross-sectional view.