Oxide Semiconductor Transistor with Angled Conductor Layers
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Solution Overview
Problem
Current transistors with oxide semiconductors face challenges in achieving low parasitic capacitance, high frequency characteristics, and stable electric properties while maintaining low off-state current and high speed operation.
Innovation Solution
A semiconductor device structure incorporating an oxide semiconductor with specific conductor and insulator configurations, including a gate electrode with oxygen-penetrating suppression capabilities, and strategically angled conductor layers to minimize parasitic capacitance and enhance frequency performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a transistor includes an oxide semiconductor with conventional conductor and insulator configurations, then it can achieve low off-state current, but it suffers from high parasitic capacitance and poor frequency characteristics
Solution Approach 1:
The patent applies local quality by creating a tilted side surface structure in the insulator layer at the interface with the gate electrode. This localized structural modification reduces the overlapping area between conductors and insulators specifically at critical regions, thereby reducing parasitic capacitance without affecting the overall transistor structure that maintains low off-state current through oxide semiconductor properties.
Solution Approach 2:
The patent introduces a dimensional change by forming a tilted side surface (angled between 30-60 degrees from vertical) in the insulator layer instead of a conventional vertical or planar interface. This angular configuration reduces the effective overlapping area between the gate electrode and source/drain electrodes, thereby reducing parasitic capacitance while maintaining electrical isolation functions.
2Ease of manufacture
If conventional transistor structures are used, then manufacturing is simpler, but frequency characteristics and high-speed operation are compromised
Solution Approach 1:
The patent changes the geometric parameter of the insulator-gate interface from a vertical or planar configuration to a tilted configuration with specific angles (30-60 degrees from vertical). This parameter change reduces parasitic capacitance values, thereby improving frequency characteristics and enabling high-speed operation while remaining compatible with existing manufacturing processes.
3Device complexity
If the insulator-gate interface is made tilted at 30-60 degrees, then parasitic capacitance is reduced and frequency characteristics improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the tilted insulator structure during the deposition or etching process itself, rather than requiring subsequent precision machining. The tilted side surface is created as an inherent feature of the film formation process, allowing angle control through process parameters (such as sputtering angle or etch direction) rather than post-processing mechanical operations.
Data Source
AI summary
A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.