Oxide Semiconductor Transistor Channel Length Control
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Solution Overview
Problem
Semiconductor devices with channels made of amorphous silicon or low-temperature polysilicon struggle with low mobility and high off-current, limiting their use in display devices, while those with single crystalline silicon have complex structures and require high-temperature processes, making them unsuitable for large glass substrates. Additionally, oxide semiconductor devices have lower mobility than low-temperature polysilicon or single crystalline silicon devices, necessitating shorter channel lengths to achieve higher on-currents, which is restricted by photolithography limitations.
Innovation Solution
A semiconductor device structure featuring multiple transistors with oxide semiconductor channels of varying lengths, where the channel length of one transistor is controlled by the thickness and tapering of an insulating layer, and the other by photolithography, allowing for both high on-current and low off-current capabilities without the limitations of traditional photolithography restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a semiconductor device uses amorphous silicon or low-temperature polysilicon as the channel, then it can be formed in a low-temperature process (600°C or lower) suitable for glass substrates, but the mobility is low and off-current is high
Solution Approach 1:
The patent changes the material parameter from conventional semiconductors (amorphous silicon, low-temperature polysilicon) to oxide semiconductor, which enables low-temperature formation while achieving low off-current characteristics. The oxide semiconductor layer is formed at 600°C or lower, maintaining compatibility with glass substrates while providing superior electrical characteristics including low off-current.
2Reliability
If a semiconductor device uses low-temperature polysilicon or single crystalline silicon as the channel, then mobility is higher and it can be used in driving circuits, but the structure becomes complicated and formation temperature increases to 500°C or higher
Solution Approach 1:
The patent changes the material parameter to oxide semiconductor, which provides high mobility comparable to low-temperature polysilicon or single crystalline silicon while enabling formation at 600°C or lower. This maintains simplicity of structure and process while achieving the desired mobility for driving circuit applications.
3Reliability
If the channel length is shortened to increase on-current in oxide semiconductor devices, then on-current performance improves, but photolithography restrictions limit the minimum achievable channel length
Solution Approach 1:
The patent transitions from planar channel configuration to a three-dimensional structure where the channel extends along the side surface of the insulating layer. This dimensional change enables precise channel length control through insulating layer thickness and side surface angle, achieving channel lengths of 1 μm or shorter while overcoming photolithography resolution limits.
Solution Approach 2:
The patent changes the channel length parameter to 1 μm or shorter and controls the insulating layer side surface angle to 45° or more. This parameter optimization achieves the required on-current performance while maintaining manufacturability through precise control of insulating layer geometry rather than relying solely on photolithography.
Data Source
AI summary
A semiconductor device includes a first transistor including a first electrode, a first insulating layer above the first electrode, the first insulating layer having a first side wall, a first oxide semiconductor layer on the first side wall, the first oxide semiconductor layer being connected with the first electrode, a first gate electrode, a first gate insulating layer, and a second electrode above the first insulating layer, the second electrode being connected with the first oxide semiconductor layer; and a second transistor including a third electrode, a fourth electrode separated from the third electrode, a second oxide semiconductor layer between the third electrode and the fourth electrode, the second oxide semiconductor layer being connected with each of the third electrode and the fourth electrode, a second gate electrode, and a second gate insulating layer.