Oxide Semiconductor Transistor Layer Structure for Stable Channel Formation
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving small variations in transistor characteristics, high reliability, favorable electrical characteristics, high on-state current, miniaturization, and low power consumption, particularly in oxide semiconductor transistors with CAAC and nc structures.
Innovation Solution
A semiconductor device structure is developed with specific layers and materials, including insulators, oxides, and conductors, where the thickness of certain layers is crucial, and the use of tantalum and indium-based oxides with controlled tantalum concentration, and excess oxygen supply to maintain channel formation region integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide semiconductor transistors with CAAC and nc structures are used, then transistor characteristics can be improved, but variations in transistor characteristics increase
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness of the first layer (0.5-1.5 nm) and second layer (0.5-1.5 nm) to reduce variations in transistor characteristics. This thickness control directly addresses the manufacturing precision issue while maintaining the reliability benefits of oxide semiconductor structures.
Solution Approach 2:
The patent implements local quality by creating a specific layered structure with different materials (first layer, second layer, first oxide, second oxide) where each layer has optimized properties for its specific function. The first and second layers are positioned at critical interfaces to locally control characteristics and reduce variations.
2Productivity
If device miniaturization is pursued, then integration density increases, but maintaining favorable electrical characteristics becomes difficult
Solution Approach 1:
The patent uses parameter changes by optimizing the thickness of insulator layers and oxide layers to maintain electrical characteristics in miniaturized devices. The specific thickness ranges (0.5-1.5 nm for first and second layers) are critical for maintaining performance at smaller device dimensions while enabling higher integration density.
3Use of energy by moving object
If power consumption is reduced, then energy efficiency improves, but on-state current decreases
Solution Approach 1:
The patent applies parameter changes by controlling the thickness and composition of oxide layers to achieve low power consumption while maintaining adequate on-state current. The optimized layer structure enables energy-efficient operation without excessive current loss.
Data Source
AI summary
A semiconductor device includes a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; first and second conductors and a third oxide over the second oxide; a second insulator over the first conductor; a third insulator over the second conductor; first and second layers; and fourth to sixth insulators. The sixth insulator includes a region in contact with a top surface of the first insulator. The first layer includes a region in contact with side surfaces of the first and second oxides, a side surface of the first conductor, and the top surface of the first insulator. The second layer includes a region in contact with the side surfaces of the first and second oxides, a side surface of the second conductor, and the top surface of the first insulator.