Oxide Transistor Charge Trap Enhancement Mode
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Manufacturing an inverter with desirable characteristics using an oxide semiconductor channel layer is difficult due to the challenge of forming a p-channel layer, as oxide semiconductor channel layers typically result in depletion-mode transistors with threshold voltages less than 0 V, making it hard to achieve enhancement-mode transistors.
Innovation Solution
A transistor design with a gate electrode and channel layer separated by a gate insulating layer that includes a charge trap region, allowing charges to be trapped and increasing the threshold voltage, thereby converting the transistor from depletion-mode to enhancement-mode, using a ZnO-based oxide channel layer and a silicon nitride gate insulating layer, and employing different structures for load and switching transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If an oxide semiconductor channel layer is used, then the transistor can be manufactured with simpler process, but the transistor becomes a depletion-mode transistor with threshold voltage less than 0 V, making it difficult to achieve enhancement-mode transistor characteristics
Solution Approach 1:
A charge trap region is formed in the gate insulating layer before the transistor operation. This preliminary charge trapping action shifts the threshold voltage to achieve enhancement-mode characteristics, allowing the oxide semiconductor transistor to function as an enhancement-mode device while maintaining the manufacturing simplicity of oxide semiconductors
Solution Approach 2:
The threshold voltage is changed from negative (depletion-mode) to positive (enhancement-mode) by introducing a charge trap region in the gate insulating layer. This parameter change is achieved through controlling the charge distribution in the gate insulating layer, transforming the transistor operating mode
2Manufacturing precision
If a Si-based channel layer is used, then enhancement-mode transistors can be easily formed, but the manufacturing process becomes more complex compared to oxide semiconductor
Solution Approach 1:
The gate insulating layer is formed as a composite structure including multiple layers (e.g., silicon oxide layer and silicon nitride layer) with different properties. The silicon nitride layer provides charge trapping capability while the silicon oxide layer provides insulation, combining multiple functions in a composite structure that enables enhancement-mode operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of enhancement-mode transistors with threshold voltages greater than 0 V, improving the characteristics of inverters and allowing for the production of logic circuits and memory devices with enhanced performance.
Implementation Method 1
a gate insulating layer between the gate electrode and the channel layer including a charge trap region; and a source electrode and a drain electrode in contact with respective ends of the channel layer, the threshold voltage of the transistor may increase as charges are trapped in the charge trap region
Data Source
AI summary
A transistor, an inverter including the transistor, and methods of manufacturing the inverter and the transistor. A gate insulating layer of the transistor has a charge trap region. A threshold voltage may be moved in a positive (+) direction by trapping charges in the charge trap region. The transistor may be an enhancement mode oxide thin-film transistor (TFT) and may be used as an element of the inverter.