Oxide Semiconductor Transistor with Non-Uniform Gate Insulator
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Solution Overview
Problem
Silicon-based power devices face limitations in withstanding high voltages and controlling large currents due to physical characteristics reaching theoretical limits, necessitating a novel semiconductor material with improved high-voltage and high-speed switching capabilities.
Innovation Solution
A transistor structure utilizing an oxide semiconductor with a modified gate insulating layer capacitance distribution to increase resistance in the channel formation region near the drain, reducing the high electric field and preventing breakdown, while maintaining mobility for large current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a high voltage is applied between source and drain to control large current, then the current control capability is improved, but a high electric field is generated in the vicinity of the drain causing breakdown
Solution Approach 1:
The gate insulating layer is designed with non-uniform thickness: a first region with greater thickness than a second region. This creates different capacitance values in different channel regions, allowing the vicinity of the drain to have higher resistance that relaxes the high electric field, while other regions maintain lower resistance for good current control
Solution Approach 2:
The capacitance of the gate insulating layer is changed by varying its thickness. The first region has larger capacitance due to greater thickness, while the second region has smaller capacitance due to lesser thickness, creating the desired resistance distribution to prevent breakdown
2Reliability
If the resistance of the channel formation region in the vicinity of drain is increased to prevent breakdown, then the breakdown resistance is improved, but the mobility may be reduced affecting current control
Solution Approach 1:
Different regions of the channel formation region are assigned different resistance characteristics through the non-uniform gate insulating layer. The vicinity of the drain has higher resistance for breakdown prevention, while other regions maintain lower resistance for good mobility and current control
Solution Approach 2:
The gate insulating layer is segmented into a first region and a second region with different thicknesses and capacitance values. This segmentation allows independent optimization of resistance characteristics in different channel regions without compromising overall device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances the transistor's resistance to breakdown and enables the control of large currents and high voltages, providing a semiconductor device that withstands high electric fields without mobility reduction.
Implementation Method 1
The gate insulating layer includes a first region which overlaps with the source electrode, a second region which overlaps with the drain electrode, a third region which is sandwiched between the first region and the second region and in contact with the first region, and a fourth region which is sandwiched between the third region and the second region. The third region has smaller capacitance than the fourth region.
Implementation Method 2
when a voltage between a source and a drain is increased in a field-effect transistor, a high electric field is generated in the vicinity of the drain
Implementation Method 3
When a gate voltage is applied, carriers are induced in the channel formation region. Then, when the gate voltage is higher than or equal to a predetermined value (threshold voltage), current flows between the source electrode and the drain electrode by the induced carriers.
Data Source
AI summary
A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.