Oxide Transistor Gate Structure for Etch Stop Channel Protection
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Solution Overview
Problem
Conventional raised source/drain (RSD) structures in oxide semiconductor devices face challenges due to low etch selectivity between c-axis aligned crystalline IGZO and amorphous IGZO, leading to over-etching and etch-induced damage, which affects mobility and reliability.
Innovation Solution
A transistor device with a capping layer and gate dielectric layer acting as an etch stop layer (ESL) to prevent over-etching, combined with a gate metal layer having a U-shape to enhance contact quality and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a timed etch process is used to etch through CAAC-IGZO and land on a-IGZO, then the gate opening can be formed, but over-etching is difficult to avoid and etch-induced damage occurs at the a-IGZO surface
Solution Approach 1:
A nitride capping layer is introduced as an intermediary between the CAAC-IGZO and a-IGZO layers. This capping layer serves as an etch stop layer that prevents the etch process from damaging the a-IGZO surface, thereby solving the over-etching problem while maintaining reliable device operation
Solution Approach 2:
The nitride capping layer is deposited in advance before the etch process to protect the a-IGZO surface. This preliminary protective action ensures that when the etch process occurs, the underlying a-IGZO is already shielded, preventing etch-induced damage before it can happen
2Adaptability or versatility
If CAAC-IGZO and a-IGZO are used with identical chemical composition, then the material system is simplified, but etch selectivity between the two materials is extremely low
Solution Approach 1:
The nitride capping layer acts as a mediator that enables selective etching. By introducing this intermediate layer with different etch characteristics, the system achieves the necessary etch selectivity without changing the underlying CAAC-IGZO and a-IGZO material composition, thus maintaining material system compatibility while solving the selectivity issue
Solution Approach 2:
The nitride capping layer is applied locally at specific positions where etch protection is needed. This localized application provides etch selectivity precisely where required (at the interface between CAAC-IGZO and a-IGZO) without affecting the overall material system properties
Data Source
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AI summary
A transistor device is provided, comprising one or more base layers, a semiconductor layer arranged on the one or more base layers, a source structure arranged on the semiconductor layer, a drain structure arranged on the semiconductor layer, and a gate structure arranged on the semiconductor layer between the source and drain structures. The gate structure comprises a dielectric layer arranged on the semiconductor layer, a gate metal layer arranged on the dielectric layer to cover a portion of the dielectric layer, and a capping layer comprising a first portion arranged on the dielectric layer between the source structure and the gate metal layer, and a second portion arranged on the dielectric layer between the gate metal layer and the drain structure. The gate metal layer is higher than the capping layer and is also higher than the dielectric layer.