Oxide Semiconductor Transistor Structure for High-Frequency Operation
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Solution Overview
Problem
Current transistors with oxide semiconductors face challenges in achieving low parasitic capacitance, high frequency characteristics, and stable electrical performance, particularly in off-state current and high-speed operation.
Innovation Solution
A transistor design incorporating an oxide semiconductor with specific conductor and insulator configurations, including overlapping regions and a silicon substrate with a (110) plane, and a concentration gradient in the channel formation region, to reduce parasitic capacitance and enhance electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional transistor structures are used, then manufacturing is easier, but parasitic capacitance is high and frequency characteristics are poor
Solution Approach 1:
The gate electrode is divided into multiple segments (first gate electrode and second gate electrode) that can be independently controlled. This segmentation allows separate optimization of different transistor regions, reducing parasitic capacitance effects while maintaining manufacturing feasibility through standardized fabrication processes
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing oxide semiconductor layers between conductive layers in a multi-layer structure. This three-dimensional arrangement reduces the horizontal footprint and parasitic capacitance while enabling high-frequency operation, transitioning from conventional planar to vertical transistor architecture
2Reliability
If oxide semiconductor transistors are used, then off-state current is low, but parasitic capacitance and frequency characteristics need improvement
Solution Approach 1:
The patent applies different material compositions and structures to specific regions: oxide semiconductor in the channel region for low off-state current, while using metal conductors and insulator arrangements in other regions to reduce parasitic capacitance. This localized optimization achieves both low leakage and high-frequency performance
Solution Approach 2:
The transistor structure combines oxide semiconductor layers with metal conductors, insulating materials, and doping regions to create a composite device. This composite approach leverages the low off-state current特性 of oxide semiconductors while incorporating materials and structures optimized for high-frequency operation
3Ease of manufacture
If simple conductor and insulator configurations are used, then manufacturing is easier, but electrical characteristics and stability are insufficient
Solution Approach 1:
The gate insulator structure serves multiple functions: electrical insulation, capacitance control, and interface quality enhancement. By designing the gate insulator with specific multi-layer configurations, the patent achieves improved electrical characteristics while maintaining compatibility with existing manufacturing processes
Data Source
AI summary
A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.