Oxide Semiconductor Transistor Gap Structure for Leakage Control

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Solution Overview

Problem

The existing OLED display panels face challenges with different types of transistors in pixel circuits, including corrosion issues and performance degradation due to the use of various materials and processes, which affect the reliability and efficiency of the display.

Innovation Solution

A display panel design that incorporates a first transistor with a silicon active layer and a second transistor with an oxide semiconductor active layer, where the conductive layers are strategically positioned to prevent corrosion and enhance performance, including specific gap widths and doping concentrations to optimize channel region formation and carrier migration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If different types of transistors are disposed in the pixel circuit to satisfy different requirements, then the functional requirements are met, but corrosion issues and performance degradation occur

Engineering Contradiction:
Improvefunctional requirements satisfactionVSAvoidcorrosion resistance and performance stability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by using different transistor types (first transistor with silicon-based active layer and second transistor with oxide semiconductor active layer) in different locations of the pixel circuit where they are most needed. The first transistor is positioned where high current driving capability is required, while the second transistor is placed where low leakage current is critical, thereby meeting functional requirements while maintaining reliability through localized optimization.

Inventive Principle:
Principle #3Local quality

2Area of stationary object

If the conductive layer is positioned close to the second gate for compact design, then the device area is reduced, but leakage current increases

Engineering Contradiction:
Improvedevice areaVSAvoidleakage current control
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent introduces an intermediary structure (the first conductive layer positioned in the non-channel region) that mediates between the second gate and the second source/drain. This intermediary conductive layer provides a controlled electrical path that reduces leakage current while maintaining compact device area, effectively solving the contradiction between miniaturization and leakage control.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If the oxide semiconductor layer is exposed to HF acid during manufacturing, then the manufacturing process is simplified, but the oxide semiconductor layer suffers corrosion and performance degradation

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidoxide semiconductor layer integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming a protective layer over the oxide semiconductor active layer before the HF acid treatment step in the manufacturing process. This protective layer prevents corrosion of the oxide semiconductor layer during subsequent manufacturing steps, thereby maintaining layer integrity while allowing the use of simplified HF-based manufacturing processes.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20220123082A1Display panel and display device
Publication Date: 2022.04.21 XIAMEN TIANMA MICRO ELECTRONICS
  • US20220123082A1 patent drawing
  • US20220123082A1 patent drawing
  • US20220123082A1 patent drawing

AI summary

Disclosed are a display panel and a display device. The display panel includes a base substrate, a first transistor, a second transistor, a first conductive layer and a second conductive layer. A second source of the second transistor is connected to a second active layer of the second transistor through the first conductive layer, a second drain is connected to the second active layer through the second conductive layer, and a second gate of the second transistor is overlapped with a channel region, the first conductive layer and the second conductive layer are located in a non-channel region, a width W1 of a first gap between the first conductive layer and the second gate is greater than 0, a width of a second gap W2 between the second conductive layer and the second gate is greater than 0.