Oxide Semiconductor Transistor Layout for Lower Field and Gate Capacitance
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Solution Overview
Problem
Miniaturization of transistors leads to increased electric field concentrations at the end portions of source and drain electrode layers, necessitating a structure that relaxes electric field concentration and reduces parasitic capacitance between the gate and source/drain electrode layers.
Innovation Solution
A transistor structure is proposed with oxide semiconductor layers, where the source and drain electrode layers have regions projecting in the channel length direction at lower end portions, and an additional insulating layer is provided between the gate and source/drain electrode layers to reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor miniaturization is implemented to achieve high-speed operation, then operation speed is improved, but electric field concentration increases at end portions of source and drain electrode layers
Solution Approach 1:
The patent applies local quality by making the source and drain electrode layers have different widths at different locations. Specifically, the electrode layers have a first width in the channel width direction that is smaller than the oxide semiconductor layer width, creating regions with different electrical characteristics. This local variation in electrode geometry reduces electric field concentration at the end portions while maintaining overall transistor functionality and high-speed operation capability.
Solution Approach 2:
The patent introduces a dimensional variation by extending the source and drain electrode layers in the channel length direction beyond the oxide semiconductor layer boundaries. This creates projecting regions that distribute the electric field over a larger area, reducing concentration effects. The electrode layers thus occupy a larger area in the channel length direction while maintaining controlled width in the channel width direction, effectively using dimensional expansion to mitigate electric field concentration.
2Speed
If transistor miniaturization is implemented to achieve high-speed operation, then device size is reduced, but parasitic capacitance between gate electrode layer and source/drain electrode layers increases
Solution Approach 1:
The patent applies local quality by creating specific geometric configurations of the source and drain electrode layers that have reduced overlap area with the gate electrode layer. The electrode layers have a first width in the channel width direction that is smaller than the oxide semiconductor layer width, which locally reduces the capacitance-forming overlap region. This selective dimensioning reduces parasitic capacitance while maintaining electrical connectivity and transistor performance.
Solution Approach 2:
The patent uses dimensional strategy by extending electrode layers in the channel length direction (adding length dimension) while controlling the channel width dimension. This dimensional redistribution reduces the overlap area between source/drain electrodes and gate in the channel width direction, thereby reducing parasitic capacitance. The extended length in channel length direction compensates for the reduced width, maintaining electrical characteristics while reducing capacitive coupling.
Data Source
AI summary
A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.